January 2007
127
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
5.4.3.1
Clock Length Matching Requirements
The 82855GME provides three differential clock pairs for each DIMM. A differential clock pair is
made up of a SCK signal and its complement signal SCK#. Refer to
for more details on
length matching requirements.
The differential pairs for one DIMM are:
SCK[0]/SCK[0]#
SCK[1]/SCK[1]#
SCK[2]/SCK[2]#
The differential pairs for the second DIMM are:
SCK[3]/SCK[3]#
SCK[4]/SCK[4]#
SCK[5]/SCK[5]#
The two sets of differential clocks must be length tuned on the motherboard such that any pair to
pair package length variation is tuned out. The three pairs associated with DIMM0 are tuned to a
fixed overall length, including package, and the three pairs associated with DIMM1 are tuned to a
fixed overall length.
Package Length Range – P1
1000 mils ± 350 mils
Refer to clock package length for exact lengths.
Trace Length Limits – L1
Max = 300 mils (breakout segment)
Length Limits – P1 + L1 + L2
Min = 3.5”
Max = 6.5”
Total Length – P1 + L1 + L2
Total length target is determined by placement
Total length for DIMM0 group = X0
Total length for DIMM1 group = X1
SCK to SCK# Length Matching
Match total length to ±10 mils
Clock to Clock Length Matching (Total Length)
Match all DIMM0 clocks to X0 ± 25 mils
Match all DIMM1 clocks to X1 ± 25 mils
Breakout Exceptions
(Reduced geometries for MCH breakout
region)
Inner Layers: 4 mil trace, 4 mil pair space allowed
Outer Layers: 5 mil trace, 5 mil pair space allowed
Pair-to-pair spacing of 5 mils allowed
Spacing to other DDR signals of 5 mils allowed
Maximum breakout length is 0.3”
Table 30. DDR Clock Signal Group Routing Guidelines (Sheet 2 of 2)
Parameter
Definition
NOTES:
1. Pad-to-pin length tuning is used on clocks to achieve minimal variance. Package lengths range between
approximately 600 mils and 1400 mils. Exact package lengths for each clock signal are provided at the
end of this section. Overall target length shall be established based on placement and routing flow. The
resulting motherboard segment lengths must fall within the ranges specified.
2. The DDR clocks shall be routed on internal layers, except for pin escapes. It is recommended that pin
escape vias be located directly adjacent to the ball pads on all clocks. Surface layer routing shall be
minimized.
3. Exceptions to the trace width and spacing geometries are allowed in the breakout region to fan-out the
interconnect pattern. Reduced spacing shall be avoided as much as possible.
Summary of Contents for 6300ESB ICH
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