Intel 6300ESB ICH, Design Manual

Page: 221 / 320

January 2007 221
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
9.8 SMBus 2.0/SMLink Interface
The SMBus interface on the 6300ESB uses two signals SMBCLK and SMBDATA to send and
receive data from components residing on the bus (see
Figure 116 ). These signals are used
exclusively by the SMBus Host Controller. The SMBus Host Controller resides inside the
6300ESB.
The 6300ESB incorporates a SMLink interface supporting Alert on LAN*, Alert on LAN2* and a
slave functionality. It uses two signals SMLINK [1:0]. SMLINK[0] corresponds to an SMBus
clock signal and SMLINK[1] corresponds to an SMBus data signal. These signals are part of the
SMB Slave Interface.
For Alert on LAN* functionality, the 6300ESB transmits heartbeat and event messages over the
interface. When using the Intel
®
82562EM/82562EX Platform LAN Connect Component, it will
claim the SMLink heartbeat and event messages and send them out over the network. An external,
Alert on LAN2*-enabled LAN Controller (e.g., Intel 82562EM/82562EX 10/100 Mbps Platform
LAN Connect) will connect to the SMLink signals to receive heartbeat and event messages, as well
as access the 6300ESB SMBus Slave Interface. The slave interface function allows an external
microcontroller to perform various functions. For example, the slave write interface may reset or
wake a system, generate SMI# or interrupts, and send a message. The slave read interface may read
the system power state, read the watchdog timer status, and read system status bits.
Table 88. LPC Interface Routing Summary
Trace
Impedance
LPC Routing
Requirements
Trace Lengths LPC Clock Length Matching
55
Ω
± 10%
5 mil width, 12 mil
spacing (based on
stackup assumptions
in
Section 3.1 )
L1 = 2 to 8 inches
L2 = 0 to 6 inches
L3 =0 to 6 inches
No more than 0.25 inches (250 mils)
difference between clock signals.