Intel 6300ESB ICH, Design Manual

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260
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Platform Clock Routing Guidelines
11.2.8 USBCLK Clock Group
The 48 MHz USBCLK is series terminated and routed point-to-point on the motherboard. This
clock operates independently and is not length tuned to any other clock.
Figure 145 depicts the
USBCLK clock topology. Table 113 presents the USBCLK clock routing constraints.
Figure 145. USBCLK Clock Topology
Table 113. USBCLK Clock Routing Constraints
Parameter Definition
Class Name USBCLK
Class Type Individual Net
Topology Series Terminated Point to Point
Reference Plane Ground Referenced
Single Ended Trace Impedance (Zo) 55
Ω
± 15%
Nominal Inner Layer Trace Width 4.0 mils
Nominal Outer Layer Trace Width 5.0 mils (pin escapes only)
Minimum Spacing (See exceptions below.) 20 mils
Maximum Via Count 4
Series Termination Resistor Value 33
Ω
± 5%
Trace Length Limits – L1 Up to 500 mils
Trace Length Limits – L2 3.0” to 12.0”
Total Length Range – L1 + L2 3.0” to 12.5”
Length Matching Required No
Breakout Exceptions 5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
L1
Rs
CK409
GMCH
L2