Intel 6300ESB ICH, Design Manual

Page: 261 / 320

January 2007 261
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Platform Clock Routing Guidelines
11.2.9 SRC Clock Group
11.2.9.1 SRC Clock Topology
The clock synthesizer provides one set of 100-MHz differential clock outputs. The differential
clocks are driven to the Intel
®
Pentium
®
M Processor and Embedded Intel
®
855GME Chipset with
Intel
®
6300ESB I/O Controller Hub for serial-ATA as shown in Figure 137 .
The clock driver differential bus output structure is a Current Mode Current Steering output that
develops a clock signal by alternately steering a programmable constant current to the external
termination resistors Rt.
The recommended termination for the differential bus clock is a Shunt Source Termination. See
Figure 146 for an illustration of this terminology scheme. Parallel Rt resistors perform a dual
function, converting the current output of the clock driver to a voltage and matching the driver
output impedance to the transmission line. The series resistors Rs provide isolation from the clock
driver’s output parasitics which would otherwise appear in parallel with the termination resistor Rt.
The value of Rt should be 49
Ω
and Rs should be 33
Ω
. Simulations have shown that Rs values
above 33
Ω
provide no benefit to signal integrity but only degrade the edge rate.
Figure 146. Source Shunt Termination
Table 114. SCR/SCR# Routing Guidelines (Sheet 1 of 2)
Layout Guideline Value Illustration Notes
Trace Width 5 mils Figure 147
Differential Pair Spacing 11 mils Figure 147 1 , 2 , 3
Spacing to Other Traces 25 mils Figure 147
Serpentine Spacing
Maintain a minimum 25 mils.
Keep parallel serpentine
sections as short as possible.
Minimize 90-degree bends.
Make 45-degree bends, if
possible.
L1'
L1
Rs
L2
L2'
L3 L3'
L4
L4'
Clock
Driver
Intel®
6300ESB
Rs
Rt Rt
LT = L1 + L2 + L4