Intel 6300ESB ICH, Design Manual

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70
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
The recommended layout of the Intel Pentium M/Celeron M processor COMP[3:0] resistors is
illustrated in
Figure 31 . To avoid interaction with Intel Pentium M/Celeron M processor FSB
routing on internal layers and VCCA power delivery on the primary side, Layer 1, COMP[1:0]
resistors are placed on the secondary side. Ground connections to the COMP[1:0] resistors use a
small ground flood on the secondary side layer and connect only with a single GND via to stitch
the GND planes. The compact layout as shown in
Figure 31 shall be used to avoid excessive
perforation of the V
CCP
plane power delivery. Figure 31 illustrates how a 27.4
Ω
resistor connects
with an ~18 mil wide (Zo = 27.4
Ω
) and 160 mil long trace to COMP0. Necking down to 14 mils is
allowed for a short length to pass in between the dog bones. The 54.9
Ω
resistor connects with a
regular 5 mil wide (Zo = 55
Ω
) and 267 mil long trace to COMP1. Placement of COMP[1:0] on the
primary side is possible as well. An alternative placement implementation is shown in Figure 32 .
To minimize motherboard space usage and produce a robust connection, the COMP[3:2] resistors
are also placed on the secondary side (
Figure 31 , right side). A 27.4
Ω
resistor connects with an
18 mil wide (Zo = 27.4
Ω
) and 260 mil long trace to COMP2. Necking down to 14 mils is allowed
for a short length to pass in between the dog bones. Notice that the COMP2 ( Figure 31 , left side)
dog bone trace connection on the primary side is also widened to 14 mils to meet the Zo = 27.4
Ω
characteristic impedance target. The right side of Figure 31 also illustrates how the 54.9
Ω
± 1%
resistor connects with a regular 5 mil wide (Zo = 55
Ω
) and 100 mil long trace to COMP3. The
ground connection of COMP[3:2] is done with a small flood plane on the secondary side that
connects to the GND vias of pins AA1 and Y2 of the Intel Pentium M/Celeron M processor
pin-map. This is done to avoid via interaction with the Intel Pentium M/Celeron M processor FSB
routing on Layer 3 and Layer 6.
For COMP2 and COMP0, it is extremely important that 18 mil wide dog bone connections on the
primary side and 18-mil wide traces on the secondary sides be used to connect the signals to
compensation resistors on the secondary side, as shown in
Figure 33 . The 18-mil wide dog bones
and traces are used to achieve the Zo = 27.4
Ω
target to ensure proper operation of the Intel
Pentium M/Celeron M processor FSB. Refer to Figure 29 for more details.
Figure 29. Intel
®
Pentium
®
M/Celeron
®
M Processor COMP[2] and COMP[0]
Resistive Compensation
Figure 30. Intel
®
Pentium
®
M/Celeron
®
M ProcessorCOMP[3] and COMP[1]
Resistive Compensation
27.4
Ω
±1%
COMP[0]
27.4
Ω
±1%
COMP[2]
54.9
Ω
±1%
COMP[3]
54.9
Ω
±1%
COMP[1]