Intel 6300ESB ICH, Design Manual

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Design Guide 175
Intel
®
855GME Chipset and Intel
®
82801DB ICH4 Embedded Platform Design Guide
AGP Port Design Guidelines
7.2 AGP Routing Guidelines
7.2.1 1x Timing Domain Routing Guidelines
7.2.1.1 Trace Length Requirements for AGP 1X
This section contains information on the 1X timing domain routing guidelines. The AGP 1X timing
domain signals (see
Table 59 ) have a maximum trace length of 10 inches. The target impedance is
55
Ω
± 15%. This maximum applies to ALL of the signals listed as 1X timing domain signals in
Table 46. In addition to the maximum trace length requirement, these signals must meet the trace
spacing and trace length mismatch requirements in
Section 7.2.1.2 and Section 7.2.1.3 .
7.2.1.2 Trace Spacing Requirements
AGP 1X timing domain signals (see Table 59 ) can be routed with 4-mil minimum trace separation.
7.2.1.3 Trace Length Mismatch
There are no trace length mismatch requirements for 1X timing domain signals. These signals must
meet minimum and maximum trace length requirements.
7.2.2 2x/4x Timing Domain Routing Guidelines
7.2.2.1 Trace Length Requirements for AGP 2X/4X
These trace length guidelines apply to ALL of the signals listed as 2x/4x timing domain signals in
Table 60 . In addition to these maximum trace length requirements, these signals must meet the
trace spacing and trace length mismatch requirements in Section 7.2.1.2 and Section 7.2.1.3 .
Table 59. Layout Routing Guidelines for AGP 1X Signals
1X signals Max. Length (inches) Width (mils) Space (mils)
CLK_AGP_SLT 10 4 4
AGP_PIPE# 10 4 4
AGP_RBF# 10 4 4
AGP_WBF# 10 4 4
AGP_ST[2:0] 10 4 4
AGP_FRAME# 10 4 4
AGP_IRDY# 10 4 4
AGP_TRDY# 10 4 4
AGP_STOP# 10 4 4
AGP_DEVSEL# 10 4 4
AGP_REQ# 10 4 4
AGP_GNT# 10 4 4
AGP_PAR 10 4 4