Intel 6300ESB ICH, Design Manual

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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
Pentium
®
M/Celeron
®
M Processor FSB Design and Power Delivery Guidelines
Refer to Section 4.1.2.1 for trace length and package compensation requirements. The two
complementary strobe signals associated with each group shall be length matched (pad-to-pin) to
each other within ± 25 mils and tuned to the average length of the data signals (pad-to-pin) of their
associated group. This optimizes setup/hold time margin.
Table 6 lists the source synchronous data signal general routing requirements. Due to the 400 MHz,
high-frequency operation the data signals shall be limited to a pin-to-pin trace length minimum of
0.50 inches and maximum of 5.5 inches.
4.1.3.2 Source Synchronous – Address Group
Source synchronous address signals operate at 200 MHz. Thus, their routing requirements are very
similar to the data signals. Refer to
Section 4.1.3 and Section 4.1.3.1 for further details. Table 7
details the partition of the address signals into matched length groups. Due to the lower operating
frequency of the address signals, pad-to-pin length matching is relaxed to ± 200 mils. Each group
is associated with only one strobe signal. To maximize setup/hold time margin, the address strobes
shall be trace length matched to the average trace length of the address signals of their associated
group. In addition, each address signal shall be trace length matched within ± 200 mils of its
associated strobe signal.
Table 5. Intel
®
Pentium
®
M/Celeron
®
M Processor FSB Data Source Synchronous Signal
Trace Length Mismatch Mapping
Data Group
DINV Signal for
Associated
Data Group
Signal
Matching
Data Strobes
Associated with the
Group
Strobe
Matching
Notes
D[15:0]# DINV0# ± 100 mils DSTBP0#, DSTBN0# ± 25 mils 1 , 2
D[31:16]# DINV1# ± 100 mils DSTBP1#, DSTBN1# ± 25 mils 1 , 2
D[47:32]# DINV2# ± 100 mils DSTBP2#, DSTBN2# ± 25 mils 1 , 2
D[63:48]# DINV3# ± 100 mils DSTBP3#, DSTBN3# ± 25 mils 1 , 2
NOTES:
1. Strobes of the same group shall be trace length matched to each other within ± 25 mils and to the average
length of their associated data signal group.
2. All length matching formulas are based on GMCH die-pad to Intel Pentium M/Celeron M Processor pin
total length per byte lane. Package length tables are provided for all signals to facilitate this pad-to-pin
matching.
Table 6. Intel
®
Pentium
®
M/Celeron
®
M Processor System Bus Source Synchronous
Data Signal Routing Guidelines
Signal Names
Trans-
mission
Line Type
Total Trace Length
Nominal
Impedance
(
Ω
)
Width
and
spacing
(mils)
Data Group #1 Data Group #2 Data Group #3 Data Group #4
Min
(inches)
Max
(inches)
D[15:0]# D[31:16]# D[47:32]# D[63:48]# Strip-line 0.5 5.5 55 ± 15% 4 and 12
DINV0# DINV1# DINV2# DINV3# Strip-line 0.5 5.5 55 ± 15% 4 and 12
DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# Strip-line 0.5 5.5 55 ± 15% 4 and 12
DSTBP[0]# DSTBP[1]# DSTBP[2]# DSTBP[3]# Strip-line 0.5 5.5 55 ± 15% 4 and 12