89
5.2.5 IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins
IRQ
5
,
IRQ
4
,
IRQ
1
, and
IRQ
0
Bit
Initial value
Read/Write
7
—
0
R/W
These bits select level sensing or falling-edge
sensing for IRQ
5
and IRQ
4
interrupts
6
—
0
R/W
5
IRQ5SC
0
R/W
4
IRQ4SC
0
R/W
3
—
0
R/W
2
—
0
R/W
1
IRQ1SC
0
R/W
0
IRQ0SC
0
R/W
IRQ and IRQ sense control
5
4
These bits select level sensing or falling-edge
sensing for IRQ
1
and IRQ
0
interrupts
IRQ and IRQ sense control
1
0
Reserved bits
Reserved bits
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7, 6, 3, and 2—Reserved: These bits are readable/writable and do not affect selection of
level sensing or falling-edge sensing.
Bits 5, 4, 1, and 0—IRQ
5
, IRQ
4
, IRQ
1
,
,
and IRQ
0
Sense Control (IRQ5SC, IRQ4SC, IRQ1SC,
IRQ0SC): These bits selects whether interrupts IRQ
5
, IRQ
4
, IRQ
1
, IRQ
0
are requested by level
sensing of pins
IRQ
5
,
IRQ
4
,
IRQ
1
,
IRQ
0
or by falling-edge sensing.
Bits 5, 4, 1, and 0
IRQ5SC, IRQ4SC,
IRQ1SC, IRQ0SC
Description
0
Interrupts are requested when
IRQ
5
,
IRQ
4
,
IRQ
1
,
IRQ
0
inputs are low
(Initial value)
1
Interrupts are requested by falling-edge input at
IRQ
5
,
IRQ
4
,
IRQ
1
,
IRQ
0