3
Feature
Description
16-bit integrated
timer unit (ITU)
•
Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10
pulse inputs
•
16-bit timer counter (channels 0 to 4)
•
Two multiplexed output compare/input capture pins (channels 0 to 4)
•
Operation can be synchronized (channels 0 to 4)
•
PWM mode available (channels 0 to 4)
•
Phase counting mode available (channel 2)
•
Buffering available (channels 3 and 4)
•
Reset-synchronized PWM mode available (channels 3 and 4)
•
Complementary PWM mode available (channels 3 and 4)
Programmable
•
Maximum 15-bit pulse output, using ITU as time base
timing pattern
controller (TPC)
•
Up to three 4-bit pulse output groups and one 3-bit pulse output group (or one 15-
bit group, one 8-bit group, or one 7-bit group)
•
Non-overlap mode available
Watchdog timer
•
Reset signal can be generated by overflow
(WDT), 1 channel
•
Reset signal can be output externally (However, not available with the F-ZTAT
version.)
•
Usable as an interval timer
Serial
•
Selection of asynchronous or synchronous mode
communication
•
Full duplex: can transmit and receive simultaneously
interface (SCI),
•
On-chip baud-rate generator
2 channels
•
Smart card interface functions added (SCI0 only)
A/D converter
•
Resolution: 10 bits
•
Eight channels, with selection of single or scan mode
•
Variable analog conversion voltage range
•
Sample-and-hold function
•
Can be externally triggered
I/O ports
•
55 input/output pins
•
8 input-only pins
Operating modes
Five MCU operating modes
Mode
Address
Space
Address
Pins
Bus
Width
Mode 1
1 Mbyte
A
0
to A
19
8 bits
Mode 3
16 Mbytes
A
0
to A
23
8 bits
Mode 5
1 Mbyte
A
0
to A
19
8 bits
Mode 6
16 Mbytes
A
0
to A
23
8 bits
Mode 7
1 Mbyte
—
—
•
On-chip ROM is disabled in modes 1 and 3
