Analog Devices SHARC ADSP-214 Series, Hardware Reference Manual, Page: 877 / 1192

ADSP-214xx SHARC Processor Hardware Reference A-51
Registers Reference
AMI Status Register (AMISTAT)
This 32-bit register provides status information for the AMI interface and
can be read at any time. This register is shown in
Figure A-22 and
described in Table A-27 .
SDRAM Registers
This section provides complete descriptions of the SDRAM controller’s
memory-mapped registers for SDRAM programming.
Control Register (SDCTL)
The SDRAM memory control register includes all programmable parame-
ters associated with the SDRAM access timing and configuration. This
32-bit register is shown in
Figure A-23 and described in Table A-28 .
Figure A-22. AMISTAT Register
Table A-27. AMISTAT Register Bit Descriptions (RO)
Bit Name Description
0 AMIMS AMI External Bus Master.
0 = SDRAM Controller controls the external bus
1 = AMI controls the external bus (default)
For ADSP-2146x processors bit 0 is always (=1) since the DDR2
and AMI are not shared
1 AMIS External Interface Status.
0 = AMI interface idle
1 = AMI access pending
15–2 Reserved
AMI S
External Interface S tatus
0 9 8 3 7 5 6 4 2 1 14 12 11 10 1 3 15
AMIM S
External Bus Master
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