manualshive.com logo in svg

Analog Devices SHARC ADSP-214 Series, Hardware Reference Manual, Page: 610 / 1192

Share
Download
Analog Devices SHARC ADSP-214 Series Hardware Reference Manual Download Page 610

Operating Modes

14-16

ADSP-214xx SHARC Processor Hardware Reference

• SRU is the input source. If the input clock and trigger signal are 

synchronous, the delay is exactly 3 input clock periods. If asyn-
chronous, it varies between 2.5 to 3.5 input clock periods 
depending on the phase difference between the input clock and 
trigger signal.

Audio System Example

Figure 14-6

 shows an example of the internal interconnections between 

the SPDIF receiver, ASRC, and the PCGs. The interconnections are made 
by programming the signal routing unit. 

It shows how to set up two precision clock generators using the S/PDIF 
receiver and an asynchronous sample rate converter (ASRC) to interface to 
an external audio DAC. The PCG is configured to provide a fixed 
ASRC/DAC output sample rate of 65.098 kHz. The input to the S/PDIF 
receiver is typically 44.1 kHz if supplied by a CD player, but can also be 
from other source at any nominal sample rate from about 22 kHz to 192 
kHz.

Similarly, the phase shift for frame syncs B, C, and D is specified in the 
corresponding 

PCG_CTLxO

 and 

PCG_CTLx1

 registers.

Three synchronous clocks are required in audio systems

1. Frame sync (

FS

)

2. Serial bit clock (64 x FS) 

3. Master DAC clock (256 x FS)

Since each PCG has only two outputs, this example requires two PCGs. 
Furthermore, because the digital audio interface requires a fixed-phase 
relation between 

SCLK

 and 

FS

, these two outputs should come from one 

PCG (PCG A) while the master clock comes from the 2nd (PCG B).

www.BDTIC.com/ADI

Summary of Contents for SHARC ADSP-214 Series

Page 1: ...Processor Hardware Reference Includes ADSP 2146x ADSP 2147x ADSP 2148x Product Families Revision 0 3 July 27 2010 Part Number 82 000469 01 Analog Devices Inc One Technology Way Norwood Mass 02062 9106...

Page 2: ...d reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted b...

Page 3: ...s Manual lxv Technical or Customer Support lxvi Registration for MyAnalog com lxvi EngineerZone lxvii Social Networking Web Sites lxvii Supported Processors lxvii Product Information lxviii Analog Dev...

Page 4: ...ing Unit 1 4 Digital Peripheral Interface DPI 1 4 Interrupt Controller 1 4 Signal Routing Unit 2 1 5 Development Tools 1 5 Differences from Previous Processors 1 5 I O Architecture Enhancements 1 6 I...

Page 5: ...on 2 22 Automated Data Transfer 2 22 DMA Transfer Types 2 23 DMA Direction 2 24 Internal to External Memory 2 24 Peripheral to Internal Memory 2 24 Peripheral to External Memory SPORTs 2 25 Internal M...

Page 6: ...2 43 SPORT External Port DMA Bus 2 43 Rotating DMA Channel Arbitration 2 44 Rotating Priority by Group 2 44 Interrupts 2 45 Sources 2 45 Unchained DMA Interrupts 2 45 Chained DMA Interrupts 2 46 Trans...

Page 7: ...Pin Multiplexing 3 3 Register Overview 3 3 Clocking AMI SDRAM 3 5 Clocking AMI DDR2 3 6 External Port Arbitration 3 7 Functional Description 3 7 Operating Mode 3 10 Arbitration Freezing 3 10 Asynchro...

Page 8: ...Register 3 20 Bank Activation 3 21 Single Precharge 3 21 Precharge All 3 22 Read Write 3 22 Auto Refresh 3 24 No Operation Command Inhibit 3 24 Command Truth Table 3 24 Address Mapping 3 25 Address T...

Page 9: ...SDRAM Read Optimization 3 40 Core Accesses 3 41 DMA Access 3 43 Notes on Read Optimization 3 43 Self Refresh Mode 3 44 Forcing SDRAM Commands 3 45 Force Precharge All 3 45 Force Load Mode Register 3...

Page 10: ...Exit 3 57 Precharge Power Down Entry 3 58 Precharge Power down Exit 3 59 No Operation Command Inhibit 3 60 Address Mapping 3 60 Address Translation Options 3 60 Page Interleaving Map 3 60 Bank Interle...

Page 11: ...3 74 Operating Modes 3 75 Parallel Connection of DDR2s 3 75 Buffering Controller for Multiple DDR2s 3 76 Read Optimization 3 76 DDR2 Read Optimization 3 77 Self Refresh Mode 3 79 Single Ended Data Str...

Page 12: ...truction Storage and Packing 3 92 Mixing Instructions and Data in External Bank 0 3 93 Addressing for Various Memory Sizes 3 93 Writing Instructions to External Memory 3 94 Instruction Cache 3 95 Fetc...

Page 13: ...DMA Mode 3 115 External Port Throughput 3 116 AMI Data Throughput 3 117 SDRAM Throughput 3 117 Throughput Conditional Instructions 3 117 DDR2 Throughput 3 118 DMA Throughput 3 118 Core Throughput 3 11...

Page 14: ...ring Runtime 3 128 DDR2 Controller 3 129 Power Up Sequence 3 129 Frequency Change in Precharge Power Down Mode 3 130 External Instruction Fetch 3 131 AMI Configuration 3 132 SDRAM Configuration 3 132...

Page 15: ...15 Core Transfers 4 15 DMA Transfers 4 16 Interrupts 4 16 Interrupt Sources 4 17 Interrupt Service 4 17 Access Completion 4 18 Internal Transfer Completion 4 18 DMA Access 4 19 Chained DMA 4 19 Core A...

Page 16: ...A Features 5 2 Register Overview 5 2 Clocking 5 2 Functional Description 5 3 Data Transfer Types 5 3 Data Buffer 5 3 DMA Transfer 5 4 Interrupts 5 4 MTM Throughput 5 5 Effect Latency 5 5 Write Effect...

Page 17: ...essing State 6 7 Write State 6 7 Internal Memory Storage 6 8 Small FFT N 256 6 8 Large FFT N 256 6 9 Operating Modes 6 11 Small FFT Computation 256 Points 6 11 Large FFT Computation 512 Points 6 11 Ex...

Page 18: ...nterrupts 6 18 Servicing MAC Status Interrupts 6 18 FFT Performance 6 19 Small FFT N is 256 6 19 Large FFT N 256 6 19 Vertical FFT cycles 6 20 Special Prod cycles 6 20 Horizontal FFT cycles 6 20 Debug...

Page 19: ...Mode 6 27 Write to Local Memory 6 27 Read from Local Memory 6 28 FIR Accelerator 6 28 Features 6 28 Register Overview 6 29 Clocking 6 29 Functional Description 6 30 Compute Block 6 31 Partial Sum Regi...

Page 20: ...Point Data Format 6 42 Fixed Point Data Format 6 42 Data Transfer 6 42 DMA Access 6 42 Chain Pointer DMA 6 43 Interrupts 6 44 Interrupt Sources 6 45 Debug Features 6 45 Local Memory Access 6 45 Singl...

Page 21: ...ng Example 6 53 IIR Accelerator 6 55 Features 6 55 Register Overview 6 55 Clocking 6 56 Functional Description 6 56 Multiply and Accumulate MAC Unit 6 59 Data Memory 6 60 Coefficient Memory 6 60 Inter...

Page 22: ...67 IIR Accelerator Effect Latency 6 67 IIR Throughput 6 67 Programming Model 6 68 Writing to Local Memory 6 69 Reading from Local Memory 6 70 Single Step Mode 6 71 Programming Example 6 71 PULSE WIDTH...

Page 23: ...ion 7 15 Output Control Feature Precedence 7 17 Operation Modes 7 18 Waveform Modes 7 18 Edge Aligned Mode 7 18 Center Aligned Mode 7 19 PWM Timer Edge Aligned Update 7 21 Single Update Mode 7 22 Doub...

Page 24: ...rs 8 4 Clocking 8 5 Functional Description 8 5 Operating Modes 8 7 Streaming Channel Frame Synchronization 8 7 Big Endian and Little Endian Mode 8 8 Data Transfer 8 8 Core Driven Data Transfer 8 8 I O...

Page 25: ...Pin Buffers as Signal Output 9 8 Pin Buffers as Signal Input 9 10 Pin Buffers as Open Drain 9 11 DAI DPI Pin Buffer Status 9 11 Unused DAI DPI Pins 9 12 Miscellaneous Buffers 9 12 DAI DPI Peripherals...

Page 26: ...ion Interrupts 9 32 Functional Description 9 33 DAI Interrupt Channels 9 33 DAI Interrupt Priorities 9 34 DPI Interrupt Channels 9 34 DPI Interrupt Priorities 9 34 DAI Miscellaneous Interrupts 9 35 DP...

Page 27: ...s 10 2 Pin Descriptions 10 4 SRU Programming 10 5 SRU SPORT Receive Master 10 6 SRU SPORT Signal Integrity 10 6 Register Overview 10 7 Clocking 10 8 Master Clock 10 8 Master Frame Sync 10 9 Slave Mode...

Page 28: ...ection 10 23 Channel Order First 10 24 Standard Serial Mode 10 25 Timing Control Bits 10 25 Clocking Options 10 26 Frame Sync Options 10 26 Framed Versus Unframed Frame Syncs 10 26 Early Versus Late F...

Page 29: ...0 36 Companding Limitations ADSP 2146x 10 37 Packed Mode 10 37 Clocking Options 10 38 Frame Sync Options 10 38 Timing Control Bits 10 39 Data Transfers 10 39 Data Buffers 10 40 Transmit Buffers TXSPxA...

Page 30: ...outing 10 54 Buffer Hang Disable BHD 10 54 Effect Latency 10 54 Write Effect Latency 10 55 SPORT Effect Latency 10 55 Programming Model 10 55 Setting Up and Starting DMA Master Mode 10 55 Setting Up a...

Page 31: ...Operating Modes 11 8 PDAP Port Selection 11 9 Data Hold 11 9 PDAP Data Masking 11 10 PDAP Data Packing 11 10 No Packing 11 10 Packing by 2 11 11 Packing by 3 11 12 Packing by 4 11 13 Data Transfer 11...

Page 32: ...w Interrupts 11 24 Debug Features 11 25 Status register Debug 11 25 Buffer Hang Disable 11 25 Shadow Registers 11 25 Core FIFO Write 11 26 Effect Latency 11 26 Write Effect Latency 11 26 IDP Effect La...

Page 33: ...on 12 5 Serial Data Ports 12 9 Operating Modes 12 9 TDM Daisy Chain Mode 12 10 TDM Input Daisy Chain 12 11 TDM Output Daisy Chain 12 11 Bypass Mode 12 12 Matched Phase Mode ADSP 21488 12 12 Data Forma...

Page 34: ...S PDIF Transmitter 13 7 Functional Description 13 7 Input Data Format 13 9 Operating Modes 13 11 Full Serial Mode 13 11 Standalone Mode 13 11 Data Output Mode 13 12 S PDIF Receiver 13 13 Functional D...

Page 35: ...13 20 Debug Features 13 21 Loop Back Routing 13 21 Effect Latency 13 21 Write Effect Latency 13 21 Programming Model 13 21 Programming the Transmitter 13 21 Programming the Receiver 13 22 Interrupted...

Page 36: ...e 14 12 Bypass Mode 14 13 One Shot Mode 14 13 External Event Trigger 14 14 External Event Trigger Delay 14 15 Audio System Example 14 16 Clock Configuration Examples 14 18 Effect Latency 14 19 Write E...

Page 37: ...ystems 15 10 Multi Master Systems 15 11 Operating Modes 15 12 Transfer Initiate Mode 15 13 SPI Modes 15 14 Slave Select Outputs 15 15 Variable Frame Delay for Slave 15 17 Data Transfers 15 18 Buffers...

Page 38: ...SPI Effect Latency 15 29 Programming Model 15 29 Changing SPI Configuration 15 29 Master Mode Transfers 15 30 Core Master Transfers 15 31 DMA Master Transfers 15 31 Slave Mode Transfers 15 32 Core Sl...

Page 39: ...Pulse Width Modulation Mode PWM_OUT 16 8 PWM Waveform Generation 16 10 Single Pulse Generation 16 11 Pulse Mode 16 12 Pulse Width Count and Capture Mode WDTH_CAP 16 12 External Event Watchdog Mode EX...

Page 40: ...ptions 17 3 SRU Programming 17 3 Register Overview 17 4 Clocking 17 4 Functional Description 17 5 Operating Modes 17 6 Serial Data Output 17 6 Parallel Data Output 17 7 Effect Latency 17 8 Write Effec...

Page 41: ...king 19 4 Functional Description 19 4 Operating Mode 19 6 Trip Count 19 6 Debug Features 19 7 Emulation Considerations 19 7 Effect Latency 19 7 Write Effect Latency 19 7 Watchdog Timers Effect Latency...

Page 42: ...Registers UARTTHR 20 10 Receive Buffer Registers UARTRBR 20 11 Core Transfers 20 12 DMA Transfers 20 13 DMA Chaining 20 14 Interrupts 20 14 Interrupt Routing 20 15 DPI 20 15 UART 20 16 DMA Interrupts...

Page 43: ...Transfers 20 24 TWO WIRE INTERFACE CONTROLLER Features 21 2 Pin Descriptions 21 3 SRU Programming 21 4 Clocking 21 4 Register Overview 21 5 Functional Description 21 6 Bus Arbitration 21 9 Start and...

Page 44: ...er Hang Disable 21 18 Loop Back Routing 21 18 Effect Latency 21 19 Write Effect Latency 21 19 TWI Effect Latency 21 19 Programming Model 21 19 General Setup 21 19 Slave Mode 21 20 Master Mode Clock Se...

Page 45: ...PLL Multiplier 22 4 PLLM Hardware Control 22 4 PLLM Software Control 22 4 PLL VCO 22 5 Output Clock Generator 22 5 Core Clock CCLK 22 6 IOP Clock PCLK 22 6 SDRAM DDR2 Clock SDCLKx DDR2_CLK 22 6 Defau...

Page 46: ...Example for Clock Management 22 12 General Notes on Power Savings 22 13 Programming Models 22 13 Post Divider 22 14 Multiplier and Post Divider Programming Model 22 15 Back to Back Bypass 22 17 SYSTEM...

Page 47: ...23 20 Link Port Booting 23 21 Kernel Boot Time 23 23 ROM Booting 23 24 Programming Model 23 24 Running Reset 23 25 Running The Boot Kernel 23 25 Loading the Boot Kernel Using DMA 23 25 Executing the B...

Page 48: ...put Specifications and Jitter 23 33 RESETOUT 23 34 Input Pin Hysteresis 23 34 Pull Up Pull Down Resistors 23 35 Memory Select Pins 23 35 Edge Triggered I O 23 35 Asynchronous Inputs 23 36 Decoupling a...

Page 49: ...47x ADSP 2148x Power Management Registers A 12 Power Management Control Registers PMCTL A 12 Power Management Control Register 1 PMCTL1 A 15 Running Reset Control Register RUNRSTCTL A 18 ADSP 2146x Ex...

Page 50: ...A 43 DDR2 Pad Control Register 1 DDR2PADCTL1 A 44 ADSP 2147x ADSP 2148x External Port Registers A 45 External Port Control Register EPCTL A 45 AMI Control Registers AMICTLx A 47 AMI Status Register A...

Page 51: ...Duty Cycle High Side Registers PWMAx PWMBx A 73 Duty Cycle Low Side Registers PWMALx PWMBLx A 74 Dead Time Registers PWMDTx A 74 Debug Status Registers PWMDBGx A 74 FFT Accelerator Registers A 74 Gene...

Page 52: ...sters A 94 MLB Global Registers A 94 Device Control Configuration Register MLB_DCCR A 94 System Status Register MLB_SSCR A 96 System Data Configuration Register MLB_SDCR A 97 System Mask Configuration...

Page 53: ...ting Unit Registers A 118 Clock Routing Control Registers SRU_CLKx Group A A 118 Serial Data Routing Registers SRU_DATx Group B A 123 Frame Sync Routing Control Registers SRU_FSx Group C A 128 Pin Sig...

Page 54: ...lect Registers MTxCSy or MRxCSy A 171 SPORT Compand Registers MTxCCSy or MRxCCSy A 172 Error Control Register SPERRCTLx A 172 SPORT Error Status Register SPERRSTAT A 174 Input Data Port Registers A 17...

Page 55: ...ters A 199 Transmit Control Register DITCTL A 199 Transmit Status Bit Registers for Subframe A B DITCHANAx Bx A 202 Transmit User Bits Buffer Registers for Subframe A B Registers DITUSRBITAx Bx A 203...

Page 56: ...Registers SRU2_INPUTx Group A A 218 Pin Assignment Signal Routing SRU2_PINx Group B A 223 Pin Enable Signal Routing SRU2_PBENx Group C A 226 DPI Pin Buffer Registers A 230 Pin Buffer Status Register D...

Page 57: ...uffer Control Registers UART0TXCTL UART0RXCTL A 251 DMA Status Registers UART0TXSTAT UART0RXSTAT A 252 Two Wire Interface Registers A 253 Master Internal Time Register TWIMITR A 253 Clock Divider Regi...

Page 58: ...egister Listing A 273 PERIPHERAL INTERRUPT CONTROL Interrupt Latency B 1 Interrupt Acknowledge B 2 Interrupt Completion B 3 Interrupt Priority B 4 Peripherals with Multiple Interrupt Vector Addresses...

Page 59: ...ADSP 214xx SHARC Processor Hardware Reference lix Contents Subframe Format C 12 Channel Coding C 14 Preambles C 15 INDEX www BDTIC com ADI...

Page 60: ...Contents lx ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 61: ...cessors from Analog Devices for use in computing communications and consumer applications Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices pro...

Page 62: ...ese include DDR2 ADSP 2146x and SDRAM ADSP 2147x ADSP 2148x Chapter 4 Link Ports ADSP 2146x Describes the two bidirectional 8 bit wide link ports which can connect to other processor or peripheral lin...

Page 63: ...apter 11 Input Data Port Discusses the function of the input data port IDP which provides a low overhead method of routing signal routing unit SRU sig nals back to the core s memory Chapter 12 Asynchr...

Page 64: ...atures Chapter 19 WatchDog Timer ADSP 2147x Describes software watchdog function which can improve system reliability by forcing the processor to a known state Chapter 20 UART Port Controller Describe...

Page 65: ...the standard audio formats used by many of the peripherals This hardware reference is a companion document to the SHARC Processor Programming Reference What s New in This Manual This is the third gen...

Page 66: ...e analog com Europe support processor china analog com China support Phone questions to 1 800 ANALOGD Contact your Analog Devices Inc local sales office or authorized distributor Send questions by mai...

Page 67: ...use this open forum to share knowledge and collaborate with the ADI support team and your peers Visit http ez analog com to sign up Social Networking Web Sites You can now follow Analog Devices SHARC...

Page 68: ...a possible errata check mark next to the title that leads to the current correction report against the manual Also note MyAnalog com is a free feature of the Analog Devices Web site that allows custom...

Page 69: ...chnical library CD go to http www analog com proces sors manuals navigate to the manuals page for your processor click the request CD check mark and fill out the order form Data sheets which can be do...

Page 70: ...tax descriptions appear within brackets delim ited by commas and terminated with an ellipse read the example as an optional comma separated list of this SECTION Commands directives keywords and featur...

Page 71: ...ion identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage In the online version of this book the word Caution appears instead of this sym...

Page 72: ...Notation Conventions lxxii ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 73: ...precision dynamic range and signal to noise ratios Because floating point DSP math reduces the need for scaling and the probability of overflow using a floating point processor can simplify algo rith...

Page 74: ...specific Automotive Reli ability reports for these models Processor Architectural Overview The ADSP 214xx processors form a complete system on a chip integrat ing a large high speed SRAM and I O perip...

Page 75: ...ble on the processors For model specific information see the product specific data sheet The I O processor can perform DMA transfers between the periph erals and internal memory at the full core clock...

Page 76: ...r the SRU provides a group of registers that define the interconnection of the DAI peripherals to the DAI pins or to other DAI peripherals Digital Peripheral Interface DPI The digital peripheral inter...

Page 77: ...ments are integrated you can move easily between editing build ing and debugging activities Differences from Previous Processors This section identifies differences between the ADSP 214xx processors a...

Page 78: ...ADSP 2116x processors This architecture incorporates two independent DMA buses versus the previous SHARC DMA controllers one peripheral DMA bus IOD0 one external port DMA bus IOD1 This allows to oper...

Page 79: ...Each DMA operation transfers an entire block of data These operations include the transfer types shown in Table 2 1 and the list that follows Table 2 1 I O Processor Specifications Feature Availabilit...

Page 80: ...lowing it to perform other operations while off chip data I O occurs as a back ground task The multi bank architecture of the ADSP 214xx internal memory allows the core and IOP to simultaneously acces...

Page 81: ...on for fixed or rotating DMA channel arbitration and between the core and DMA DMA Channel Registers The following sections provide information on the registers that control all DMA operations for each...

Page 82: ...ter to the next internal memory DMA read or write location All internal index addresses are based on an internal memory offset of 0x80000 Table 2 2 Index Registers Register Name Width Bits Description...

Page 83: ...R 19 MTM Read IIEP0 1 19 External Port0 1 EIEP0 1 28 External Port external Table 2 3 Modify Registers Register Name Width Bits Description IMSP0 7A 16 SPORTA IMSP0 7B 16 SPORTB IMSPI 16 SPI IMSPIB 16...

Page 84: ...FT input OMFFT 16 Accelerator FFT output IMMTMW 16 MTM Write IMMTMR 16 MTM Read IMEP0 1 16 External Port EMEP0 1 27 External Port external Table 2 4 Count Registers Register Name Width Bits Descriptio...

Page 85: ...see DMA Chaining on page 2 32 ICIIR 16 Accelerator IIR data input CCIIR 16 Accelerator IIR coeff input OCIIR 16 Accelerator IIR output ICFFT 16 Accelerator FFT input OCFFT 16 Accelerator FFT output I...

Page 86: ...define the length of the circular buffer to be transferred to from memory on the corresponding DMA channel CPFIR 20 Accelerator FIR CPIIR 20 Accelerator IIR CPIFFT 21 Accelerator FFT input CPOFFT 20...

Page 87: ...el gets defined For more information see Chapter 8 Media Local Bus Table 2 7 Length Registers Register Name Width Bits Description ILFIR 19 Accelerator FIR input OLFIR 19 Accelerator FIR output ILIIR...

Page 88: ...cription TXSP0 7A 2 SPORTA Transmit TXSP0 7B 2 SPORTB Transmit RXSP0 7A 2 SPORTA Receive RXSP0 7B 2 SPORTB Receive TXSPI 2 SPI Transmit TXSPIB 2 SPIB Transmit RXSPI 2 SPI Receive RXSPIB 2 SPIB Receive...

Page 89: ...essor address regis ters the chain pointer register s value is offset to match the starting address of the processor s internal memory before it is used by the I O processor On the SHARC processor thi...

Page 90: ...current TCB 1 interrupt after current TCB Table 2 11 SPORT Chain Pointer Register CPSPx Bit Name Description 18 0 IIx address Next chain pointer address bits 18 0 of the chain pointer 19 PCI Program c...

Page 91: ...nt DMA channel priorities versus interrupt priorities The PCI bit only effects DMA channels that have chaining enabled Also interrupt requests enabled by the PCI bit are maskable with the IMASK regist...

Page 92: ...ports programs cannot insert a TCB in an active chain Table 2 15 shows the required TCBs for chained DMA Table 2 14 SPORT TCBs Address Register CP 27 0 CPSPx Chain Pointer CP 27 0 0x1 ICSPx Internal...

Page 93: ...supports both single and chained DMA Table 2 17 shows the required TCBs for chained DMA Table 2 16 UART0 TCBs Address Register CP 18 0 RXCP_UAC0 TXCP_UAC0 Chain Pointer CP 18 0 0x1 RXC_UAC0 TXC_UAC0...

Page 94: ...r coefficient loading continues until the number of coefficients equal to the tap length are read This is true even if the CCFIR register reaches zero as in the case of a tap length 10 and the CCFIR f...

Page 95: ...B loads five parameters for the coefficients IIRCTL2 CIIIR CMIIR CCIIR and CPIIR The second loads 10 parameters for the data IIRCTL2 IIIR IMIIR ICIIR IBIIR OIIIR OMIIR OCIIR OBIIR and CPIIR Table 2 19...

Page 96: ...CPIFFT indicates whether the TCB is for loading data or coefficients For coefficient TCBs COEFFSEL 1 circular buffering and the input length ILFFT and base length IBFFT TCB fields are ignored Table 2...

Page 97: ...the required TCBs for chained DMA The order the descriptors are fetched with circular buffering enabled is shown in Table 2 23 Table 2 22 External Port TCBs Address Register CP 18 0 CPEP CP 18 0 0x1...

Page 98: ...oading is transparent to the application The order the descriptors are fetched with circular buffering enabled is shown in Table 2 24 Table 2 24 External Port TCBs for Delay Line DMA Address Register...

Page 99: ...Scatter Gather DMA Address Register CP 18 0 CPEP CP 18 0 0x1 TPEP CP 18 0 0x2 TCEP CP 18 0 0x3 EMEP CP 18 0 0x4 EIEP CP 18 0 0x5 ICEP CP 18 0 0x6 IMEP CP 18 0 0x7 IIEP Table 2 26 External Port TCBs fo...

Page 100: ...t ing source or destination address an address modifier and a word count the processor is ready to start the DMA The peripherals each have a DMA enable bit in their channel control reg isters Setting...

Page 101: ...MA Chained DMA Chained DMA sequences are a set of multiple DMA operations each autoinitializing the next in line To start a new DMA sequence after the current one is finished the IOP automatically loa...

Page 102: ...d in the following sections Internal to External Memory DMA transfers between internal memory and external memory devices use the processor s external port For these types of transfers the application...

Page 103: ...data between internal memory locations DMA Controller Addressing Figure 2 1 shows a block diagram of the I O processor s address generator DMA controller Standard DMA Parameter Registers on page 2 4...

Page 104: ...INTERNAL MEMORY ADDRESS DMA ADDRESS GENERATOR INTERNAL ADDRESSES LOCAL BUS COUNT CHAIN POINTER MUX DMA WORD COUNTER 1 WORKING REGISTER INDEX ADDRESS POST MODIFY LOCAL BUS EXTERNAL MODIFIER EXTERNAL C...

Page 105: ...m internal memory the I O processor adds the modify value to the index register to generate the address for the next DMA transfer and writes the modified index value to the index register The modify v...

Page 106: ...RTs to the external memory space This transfer uses the 28 bit IIxSPx register DMA Channel Status There are two methods the processor uses to monitor the progress of DMA operations interrupts which ar...

Page 107: ...sequent DMA blocks Note that polling the DMA status registers especially chained DMA reduces I O bandwidth DMA Start and Stop Conditions The difference between single DMA and chained DMA is based on t...

Page 108: ...ormation on IOP operating modes The SHARC processor contains two independent 32 bit DMA buses Figure 2 2 The IOD0 bus is used for the peripherals to the internal memory and the IOD1 bus is used for ex...

Page 109: ...s an internal DMA request The I O processor prioritizes the request with all other valid DMA requests When a channel becomes the highest priority requester the I O processor asserts the channel s inte...

Page 110: ...ence comes from the chain pointer register that points to the next set of DMA parameters stored in the processor s internal memory In chained DMA operations the processor automatically initializes and...

Page 111: ...e end of the chain no further TCBs are loaded is indicated by a TCB with a chain pointer register value of zero The address field of the chain pointer registers is only 19 bits wide If a program write...

Page 112: ...aining Chained DMA operations may only occur within the same chan nel The processor does not support cross channel chaining Starting Chain Loading A DMA sequence is defined as the sum of the DMA trans...

Page 113: ...MA sequence This allows a DMA channel to have chaining disabled chain pointer register address field 0x0 until some event occurs that loads the chain pointer register with a non zero value Writing all...

Page 114: ...memory address block conflict with the IOD0 peripherals bus Otherwise the IOD1 bus operates fully independently Also note the external port DMA channel changes priority depending on the external index...

Page 115: ...2B CPSP2B RXSP2B or TXSP2B Serial Port 2B Data 8 C SPCTL5 SPMCTL5 IISP5A IMSP5A CSP5A CPSP5A RXSP5A or TXSP5A Serial Port 5A Data 9 IISP5B IMSP5B CSP5B CPSP5B RXSP5B or TXSP5B Serial Port 5B Data 10 S...

Page 116: ...1 Serial Input DAI IDP Channel 1 14 IDP_DMA_I2 IDP_DMA_M2 IDP_DMA_C2 IDP_DMA_I2A IDP_DMA_I2B IDP_DMA_PC2 Serial Input DAI IDP Channel 2 15 IDP_DMA_I3 IDP_DMA_M3 IDP_DMA_C3 IDP_DMA_I3A IDP_DMA_I3B IDP_...

Page 117: ..._PC7 Serial Input DAI IDP Channel 7 20 E SPICTL SPIDMAC SPIBAUD SPISTAT IISPI IMSPI CSPI CPSPI RXSPI or TXSPI and DMA Buffer SPI Data 21 51 F MLB_xCR Local SRAM Buf fer MLB Data 52 G SPICTLB SPIDMACB...

Page 118: ...SP 2146x only 58 LCTL1 LSTAT1 IILB1 IMLB1 ICLB1 CPLB1 TXLB0 or RXLB0 Link Port 1 Data ADSP 2146x only 59 L SPCTL7 SPMCTL7 IISP7A IMSP7A CSP7A CPSP7A RXSP7A or TXSP7A Serial Port 7A Data 60 IISP7B IMSP...

Page 119: ...FT IMFFT ICFFT IBFFT CIFFT CMFFT CLFFT CPIFFT 64 N PMCTL1 FIRCTL1 FIRCTL2 FIRMACSTAT FIRDMASTAT OIFIR OMFIR OCFIR OBFIR COFIR CMFIR CLFIR CPFIR Accelerator Out put Buffers and FIFO FIR IIR FFT Acceler...

Page 120: ...or clearing DCPR bit in the SYSCTL register as follows 0 fixed arbitration default 1 rotating arbitration IOD1 External Port Bus 65 Q DMAC0 IIEP0 IMEP0 ICEP0 EIEP0 EMEP0 ELEP0 EBEP0 RIEP0 RCEP0 RMEP0...

Page 121: ...a fixed or rotating algorithm by setting or clearing the DMAPR bits in the EPCTL regis ter as follows 10 fixed arbitration channel 0 high 11 rotating arbitration default Note the independency is only...

Page 122: ...hannel group Rotating Priority by Group In the rotating priority scheme the default priorities at reset are the same as that of the fixed priority However the peripheral priority is deter mined by gro...

Page 123: ...errupt driven DMA programs use the interrupt mask bits in the IMASK LIRPTL DPI_IMASK DAI_IMASK_x registers to selectively mask DMA channel interrupts that the I O processor latches into the IRPTL LIRP...

Page 124: ...st word of frame N becomes zero the PCI interrupt is latched At the same time the DMA reloads the TCB for that specific channel assuming no higher priority DMA requests Finally the DMA channel resumes...

Page 125: ...ed Access Completion A DMA complete interrupt is generated when accesses are finished For an external write DMA the DMA complete interrupt is generated only after the external writes on the DMA extern...

Page 126: ...ties can be re assigned by dedicated settings of the PICRx registers Table 2 29 Default Channel vs Interrupt Priorities Programmable Interrupt Default Interrupt Priority Priorities DMA Channel Priorit...

Page 127: ...breakpoints on the IOD address buses allows DMA related breakpoints For more infor mation see the VisualDSP tools documentation and the SHARC Processor Programming Reference Effect Latency The total...

Page 128: ...Processor TCB Chain Loading Access Chained TCB Type TCB Size Number of Core Cycles SPI DMA SPORT DMA1 Link port DMA 1 If the TCB for a SPORT is located in external memory additional access cycles are...

Page 129: ...ter 1 Clear all relevant registers DMA peripheral control chain pointer 2 Determine interaction method enable IRQEN IMASK setting or sta tus polling 3 Define the DMA channels interrupt priority PICR r...

Page 130: ...Programming Model 2 52 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 131: ...External Port Specifications Feature AMI SDRAM Interface DDR2 Interface Connectivity Multiplexed Pinout Yes External Port Yes External Port No SRU DAI Required No No No SRU DAI Default Routing N A N A...

Page 132: ...erface which communicates with SRAM FLASH and other devices that meet the standard asyn chronous SRAM access protocol A SDRAM controller that supports a glue less interface with any of the standard SD...

Page 133: ...ssor specific data sheet Pin Multiplexing The address data and memory select pins are multiplexed for the AMI and the SDRAM controller but not for the DDR2 controller For more information on multiplex...

Page 134: ...RAM control parameters or as a debug aid SDRAM Refresh Rate Control Register SDRRC Provides a flexible mechanism for specifying auto refresh timing DDR2CTL0 register contains the bits that control the...

Page 135: ...rs DLL1 0STAT0 After the built in DLL has started the bits return the status if the DLL has locked A control reg ister is responsible for each data byte DDR2 Pad Control Registers DDR2PADCTL1 0 If the...

Page 136: ...ble of running up to core clock 2 speed CCLK 2 and can run at various frequencies depending on the programmed DDR2 clock DDR2_CLK to core clock CCLK ratios For information processor instruction rates...

Page 137: ...ng between core and DMA access to improve fairness of bus ownership Functional Description The external port has four ports for communication Peripheral core bus for control of external port IOP regis...

Page 138: ...act as peripherals to the external world and as such they are responsible for filling the buffers with data based on the protocol used The external port also keeps track of the two DMA channels which...

Page 139: ...ority or high low priorities 2 Winning DMA channel arbitrating with SPORT DMA groups 3 Winning DMA channel arbitrating with core access In the EPCTL register the EBPR and DMAPR bits define the priorit...

Page 140: ...reezing can improve the data throughput By setting the freeze bits FRZDMA FRZCR and FRZSP each channel request is frozen for programmed accesses For example if the processor core is frozen for 32 acce...

Page 141: ...up to 6 2M words and banks 1 2 and 3 can accommodate up to 8M words each ADSP 2147x and ADSP 2148x Bank 0 can accommodate up to 2M words and banks 1 2 and 3 can accommodate up to 4M words each ADSP 21...

Page 142: ...beginning of the read access period and after the 3rd cycles AMI_RD deasserts 3 At the beginning of the hold period read data is sampled on the rising edge of the SDCLK clock 4 At the end of the hold...

Page 143: ...ous Writes AMI_ACK AMI_DATA STROBE SETUP FOR ACK AMI_RD AMI_ADDR AMI_MSx READ STROBE SETUP 1 CYCLE READ WAIT STATES WS READ HOLD WAIT STATES WHS ADDRESS SETUP FOR ACK AMI_ACK AMI_DATA STROBE SETUP ACK...

Page 144: ...a minimum of 1 idle cycle is inserted for reads even if they are from the same bank In order to achieve better read throughput an idle cycle should be programmed as 0 For more information refer to th...

Page 145: ...Figure 3 3 and Figure 3 4 If ACK is not enabled the mini mum value for WS is 2 a wait state value of 0 corresponds to 32 wait cycles If ACK is enabled the minimum allowed value for WS is 1 Table 3 3 A...

Page 146: ...uplication of the 2nd to last read with the same address Note that this redundant read does not update the memory location Table 3 4 Data Packing Bit Settings PKDIS Packing Mode PKDIS Bit Setting MSWF...

Page 147: ...predictive read is omitted The PREDIS bit bit 21 is a global bit that when set in any of the AMICTLx registers provides access to all memory banks SDRAM Controller ADSP 2147x ADSP 2148x The SHARC pro...

Page 148: ...SDRAM Allows independent auto refresh while the asynchronous memory interface AMI has control of the external port Supports self refresh mode for power savings Predictive data accesses for higher rea...

Page 149: ...ed into the column address next bits are mapped into the row address and the final two bits are mapped into the internal bank address If ADDRMODE 1 the lowest bits are mapped into the column address n...

Page 150: ...l closes all internal banks preceding any auto refresh command Activate activates a page in the required internal SDRAM bank Read write Auto refresh causes the SDRAM to execute an internal CAS before...

Page 151: ...he first SDCLK cycle following load mode reg ister the SDC issues only NOP commands to satisfy the tMRD specification Bank Activation The bank activation command is required for first access to any in...

Page 152: ...n bank after a page miss detection Read Write This command is executed if the next read write access is in the present active page During the read command the SDRAM latches the column address The dela...

Page 153: ...essors Figure 3 5 Write Timing Diagram Figure 3 6 Read Timing Diagram SDCLK COMMAND ACT ACT NOP NOP PRE WR WR WR WR NOP COL COL COL COL A A A A D D D D ROW A ROW A tRAS tRCD tRP tWR tRC ADDR BA 1 0 DA...

Page 154: ...ommand to all external banks The next activate command is not given until the tRFC specification tRFC tRAS tRP is met Auto refresh commands are also issued by the SDC as part of the power up sequence...

Page 155: ...0 in the following sections Table 3 5 SDRAM Pin States During SDC Commands Command SDCKE n 1 SDCKE n MS3 0 SDRAS SDCAS SDWE SDA10 Addresses Mode register set 1 1 0 0 0 0 Opcode Opcode Activate 1 1 0...

Page 156: ...d and all the addresses are sequential If using delay line DMA mode the addresses for a long delay line are all sequential simplifying the addressing Moreover SDRAM sequential addressing provides maxi...

Page 157: ...Internal Banks The controller assumes the SDRAM is com prised of four bank devices However SDRAM can use two bank devices by not connecting the ADDR18 pin Figure 3 7 Core Address Mapping Page and Ban...

Page 158: ...ts only 32 bit data accesses If X16DE is enabled 1 the SDC performs two 16 bit accesses to get and place 32 bit data The SDC takes the IA address and appends one extra bit to the LSB to generate the a...

Page 159: ...Address Bank Address Pins of SDRAM A 18 IA 10 BA 1 A 17 IA 9 BA 0 A 13 A 12 IA 23 A 12 A 11 IA 22 A 11 SDA10 1 b0 IA 21 A 10 A 9 IA 8 IA 20 A 9 A 8 IA 7 IA 19 A 8 A 7 IA 6 IA 18 A 7 A 6 IA 5 IA 17 A...

Page 160: ...age Interleaving Map 2K Page Size Pin Column Address Row Address Bank Address Pins of SDRAM A 18 IA 23 BA 1 A 17 IA 22 BA 0 A 13 A 12 A 11 IA 9 IA 21 A 11 SDA10 1 b0 IA 20 A 10 A 9 IA 8 IA 19 A 9 A 8...

Page 161: ...Map 1K Page Size Pin Column Address Row Address Bank Address Pins of SDRAM A 18 IA 10 BA 1 A 17 IA 9 BA 0 A 13 A 12 IA 23 A 12 A 11 IA 22 A 11 SDA10 IA 21 A 10 A 9 IA 8 IA 20 A 9 A 8 IA 7 IA 19 A 8 A...

Page 162: ...a period based on the value programmed into the lower 12 bits of this register This coordinates the supplied clock rate with the SDRAM device s required refresh rate Table 3 10 Page Interleaving Map...

Page 163: ...ddresses in SDRAM refresh cycles to refresh whole SDRAM tRAS Active to precharge time SDTRAS bits in the SDRAM mem ory control register in number of clock cycles tRP RAS to precharge time in the SDRAM...

Page 164: ...dors use separate timing specifica tions for the row active time tRC and row refresh time tRFC The controller does ignore the tRFC spec For auto refresh it use the equation tRC tRAS tRP However since...

Page 165: ...our pages This is because the absence of latency allows switching between these open pages as compared to one page in only one bank at a time Any access to any closed page in any opened bank A D force...

Page 166: ...external bank 0 and using bank interleaving SDADDRMODE bit 0 has the following logical map 0x200000 logical start address int bankA 0x2000FF logical end address int bankA 0x300000 logical start addres...

Page 167: ...ices Those that are user configurable can be found in SDRAM Registers on page A 51 Fixed Timing Parameters The timing specifications below are fixed by the controller tMRD mode register delay Required...

Page 168: ...y other peripheral the SDRAM controller can be reset by a hard or a soft reset A hard reset puts the PLL in bypass mode where the SDRAM clock runs at a lower frequency A soft reset also causes data lo...

Page 169: ...l lines feed the parallel parts as shown in Figure 3 10 Buffering Controller for Multiple SDRAMs If using multiples SDRAMs or modules the capacitive load will exceed the controller s output drive stre...

Page 170: ...niprocessor System With Multiple Buffered SDRAM Devices DATA 3 0 DQM S MS3 RAS CAS SDWE SDCLK SDCKE C O N T R O L A D D R E S S REGISTERED BUFFERS I0 I5 I4 I2 I1 O0A O4A O3A O2A O1A OXA 12 0 RAS CAS W...

Page 171: ...n 32 locations in the boundary of the external banks should not be used These locations can be used without optimization enabled If SDMODIFY 2 then 64 locations cannot be used at the bound aries of th...

Page 172: ...d efficiently using core accesses All reads are on the same page and it takes 1184 cycles to perform 512 reads Without read optimization 512 reads use 6144 processor cycles if all of the reads are on...

Page 173: ...e core and the DMA engine take advantage of the major improvements during reads using read optimization However in situations where both the core and DMA need to read from different internal memory ba...

Page 174: ...specification tXSR tRAS tRP and then issues an auto refresh command After the auto refresh command the SDC waits for the tRFC specification tRFC tRAS tRP to be met before executing the activate comma...

Page 175: ...f refresh request is issued during any external port DMA the SDC grants the request with the tRAS cycle and continues DMA operation afterwards Forcing SDRAM Commands The SDC does have some specific bi...

Page 176: ...ely executed not wait ing until the refresh counter has expired This is useful for test purposes but also to synchronize the refresh time base with a system relevant time base DDR2 DRAM Controller ADS...

Page 177: ...he DDR2 Uses a programmable refresh counter to coordinate between vary ing clock frequencies and the DDR2 s required refresh rate Provides multiple timing options to support additional buffers between...

Page 178: ...reference signal called the data strobe signal or DQS which is sampled by the receiver and used to latch the data accordingly Therefore the architecture is enhanced into three blocks in order to fulf...

Page 179: ...h the JEDEC specification and provided to the controller During a memory write the data strobe DDR2_DQS1 0 signal to the DDR2 is delayed by a fixed amount Note there are stringent timing requirements...

Page 180: ...gly During a DRAM write the DDR2 controller performs the multiplexing of positive and negative edge data This in turn is driven onto DQ as write data when the write path in the memory I O buffers is a...

Page 181: ...ient since the controller needs to mask unwanted data DDR2 Commands This section provides a description of each of the commands that the DDR2 controller uses to manage the DDR2 interface These command...

Page 182: ...rt the power up sequence no dummy access are required set the DDR2PSS bit 1 Load Extended Mode Register This command initializes DDR2 operation parameters other than those controlled by mode register...

Page 183: ...register are loaded into the EMR3 register during power up 1 Bits 13 0 always zero OCD exit 2 Bits 15 14 10 for EMR3 The DDR2 controller does not support off chip driver OCD cal ibration Also note tha...

Page 184: ...esh or during the power up sequence the controller always issues the precharge command to all internal DDR2 banks For eight bank devices the tFAW period must be satisfied while performing the precharg...

Page 185: ...address Write latency WL is defined by a read latency RL minus one and is equal to AL CL 1 and is the number of clocks of delay that are required from the time the write command is registered to the c...

Page 186: ...en The controller generates an auto refresh command after the refresh counter times out The RDIV value in the DDR2RRC register must be set so that all addresses are refreshed within the tREF period sp...

Page 187: ...stem during self refresh they can be stopped by setting the DIS_DDR2CTL bit in the DDR2CTL0 control register This reduces the power consumption in a sys tem and is shown in the following code example...

Page 188: ...for the tRFC specification to be met before executing the activate command for the transfer that caused the DDR2 to exit self refresh mode For example ustat1 dm DDR2CTL0 bit clr ustat1 DIS_DDR2CTL dm...

Page 189: ...erval of tREFI can be extended up to 8 tREFI Consult the DDR2 data sheet for complete information This mode is useful if the DDR2 operation is idling only for a short period of time This time is limit...

Page 190: ...access DDR2 the DDR2 controller multiplexes the internal 32 bit non multiplexed address into three portions Row address bits Column address bits Bank address bits The non multiplexed address that is...

Page 191: ...is is shown in Figure 3 15 One advantage of bank interleaving is that the effective page size is also up to four pages assuming four banks activated but the addresses of the four pages are not sequent...

Page 192: ...controller determines the internal DDR2 page size from the X16DE and DDR2CAW parameters Page sizes of 256 512 1K 2K and 4K words are supported The mapping of the addresses depends on the row address w...

Page 193: ...ble 3 12 through Table 3 15 also show the mapping of the internal address IA to the external address The mapping of the address depends on row address width column address width the number of internal...

Page 194: ...leaving SHARC Pin Column Address Row Address Bank Address DDR2 Pin DDR2_BA1 IA 11 BA 1 DDR2_BA0 IA 10 BA 0 DDR2_ADDR 13 DDR2_ADDR 12 A 12 DDR2_ADDR 11 IA 9 IA 23 A 11 DDR2_ADDR 10 IA 22 A 10 DDR2_ADDR...

Page 195: ...IA 23 BA 2 DDR2_BA1 IA 22 BA 1 DDR2_BA0 IA 21 BA 0 DDR2_ADDR 12 A 12 DDR2_ADDR 11 IA 20 A 11 DDR2_ADDR 10 IA 19 A 10 DDR2_ADDR 9 IA 8 IA 18 A 9 DDR2_ADDR 8 IA 7 IA 17 A 8 DDR2_ADDR 7 IA 6 IA 16 A 7 DD...

Page 196: ...is register which coordinates the supplied clock rate with the DDR2 device s required refresh rate Table 3 15 16 bit Address Mapping 4 Banks Bank Interleaving SHARC Pin Column Address Row Address Bank...

Page 197: ...ge auto refresh period in us Note tREFI tREF Number of row addresses tRAS Active to precharge time DDR2_RAS bit in the DDR2CTL1 reg ister in number of clock cycles tRP RAS to precharge time in the DDR...

Page 198: ...this pin is significant based on the fact that the minimum burst length is 4 and a burst is not divisible The DDR2_DM1 0 pins are used to mask the data on both edges of the DQS signal during writes i...

Page 199: ...o disable the controller and its I O pads In the DDR2PADCTL0 register bits 9 19 and 29 and DDR2PADCTL1 register bits 9 and 19 set 1 all the PWD bits to power down the pad receivers Initialization Sequ...

Page 200: ...for tMRD period 13 Wait for the 200 cycle counter to expire before performing any read operation 14 Start the calibration of the DLL within the processor s DDR2 controller The DDR2 is now ready for n...

Page 201: ...s falls into the address space of the other banks B C D E F or H the controller leaves bank A open and activates any of the other banks B C D E F or H Bank A to bank B active time is controlled by tRR...

Page 202: ...r It is accept able to have more than 4 banks open simultaneously but the additional ACT command s must be spaced out past the tFAW min window As shown in Figure 3 17 tRCD for the fourth opened bank i...

Page 203: ...onnected to external bank 0 has a logical mapping as follows Page Interleaving DDR2ADDRMODE bit 0 0x200000 logical start address int bankA 0x2001FF logical end address int bankA 0x200200 logical start...

Page 204: ...t bankD 0xE001FF logical end address int bankD 0x1200000 logical start address int bankE 0x12001FF logical end address int bankE 0x1600000 logical start address int bankF 0x16001FF logical end address...

Page 205: ...eter is fixed to tXSRD 200 cycles The DDR2 controller controls the following ODT related timing parame ters no user programming is required tANPD ODT to power down entry latency tAXPD ODT to power dow...

Page 206: ...der to bypass this problem an external register SSTL18 class can be used for decoupling by setting bit 24 in DDR2CTL0 register This adds a cycle of data buffering to read and write accesses Read Optim...

Page 207: ...ead optimization enabled 32 sequential reads with offsets ranging from 0 to 15 take only 40 DDR2CLK cycles Read optimization should not be enabled while reading at the external bank boundaries For exa...

Page 208: ...t read optimization 1024 reads use 5125 processor cycles if all of the reads are on the same page non sequential reads takes 9220 cycles With read optimization Listing 3 5 1024 reads take 10262 cycles...

Page 209: ...o choose whether or not to use optimization Note that from a throughput prospec tive external port arbitration also is a factor A good rule is that the requester with the higher priority should have t...

Page 210: ...re read memory System clock during self refresh mode Note that the DDR2CLK is not dis abled by the controller during self refresh mode However software may disable the clocks by setting the DIS_DDR2CT...

Page 211: ...of DDR2_DQS crossing at VREF In differential mode these timing relationships are measured relative to the crosspoint of DDR2_DQSS and its complement DDR2_DQS This distinction in timing methods is guar...

Page 212: ...re read latency is defined as the sum of additive latency plus CAS latency RL AL CL Read or write operations using AL allow seamless bursts refer to seamless operation timing diagram examples in read...

Page 213: ...se Force Extended Mode Register 1 3 Programs use the Force extended mode register 1 3 commands DDR2CTL0 register by setting bit 23 1 for EMR1 command settings DDR2CTL3 register bit 12 1 for EMR2 comma...

Page 214: ...full packed word is received the internal status signal is deasserted and new reads are allowed The AMI provides the interface to the external data pins as well as to the processor core or to the int...

Page 215: ...uffer DFEP1 0 Each data buffer is 6 locations deep and its status can be read in the DMACx register Note the DMA channels are valid for AMI SDRAM or DDR2 transfers For more information see External Po...

Page 216: ...from N and N 1 irrespective of whether N is an odd or an even address The memory controller then packs the data into 64 bits and sends it back along the core buses For a SIMD write the controller unpa...

Page 217: ...es the explicit 32 bit access which results in the physi cal space in 2x16 bit words while the 2nd 32 bit access dperforms the implicit transfer In total there is one read or write command per burst o...

Page 218: ...essors support direct fetch of instructions from external memory using the 16 bit external port Fetching is supported from external mem ory bank 0 space which is selected by MS0 This external memory c...

Page 219: ...From External Memory The SDRAM DDR2 controllers along with the processor core incorpo rates appropriate enhancements so that instruction code can be fetched from the SDRAM DDR2 at the maximum possibl...

Page 220: ...ly bank0 can be populated for external instruction fetch 16 Bit Instruction Storage and Packing In Table 3 19 the logical to physical translation is a multiplication by a factor of 3 and N 0x355554 Th...

Page 221: ...0000 0x60 0000 Instr0 15 0 0x60 0001 Instr0 31 16 0x60 0002 Instr0 47 32 0x20 0001 0x60 0003 Instr1 15 0 0x60 0004 Instr1 31 16 0x60 0005 Instr1 47 32 0x20 0002 0x60 0006 Instr2 15 0 0x60 0007 Instr2...

Page 222: ...ping 8 Bit AMI Logical ISA Normal Word Address Program Sequencer Physical Address External Bus Data7 0 0x20 0000 0xC0 0000 Instr0 7 0 0xC0 0001 Instr0 15 8 0xC0 0002 Instr0 23 16 0xC0 0003 Instr0 31 2...

Page 223: ...0 logical address 0x0020 0000 correspond ing to physical address 0x0060 0000 and ending at logical address 0x002007FF corresponding to physical address 0x0060 17FF then data buffers can be placed sta...

Page 224: ...ch ensures that the memory is used efficiently For every 2 fetches VISA or instructions ISA 3 memory accesses are required For more information refer to the Visual DSP tools loader file documentation...

Page 225: ...ache architecture mean that the functionality of the cache remains intact for execution from internal memory whereas it behaves as instruction cache for external memory execution Every instruction tha...

Page 226: ...s fetched from external memory there is a cache miss when the sequencer looks for this instruction within the cache Consequently the instruction has to be fetched from external memory and a copy of in...

Page 227: ...frees up the external port as well as the internal PM and DM buses for other operations such as data transfers operand fetches or DMA transfers The following example shows the innermost loop of a FIR...

Page 228: ...ory Fetching VISA Instructions From External Memory The SHARC processors support fetching instructions from external SDRAM or DDR2 memory These instructions may be stored either as traditional 48 bit...

Page 229: ...he addresses in range 0x20 0000 0x5F FFFF to 0x60 0000 0x11F FFFF when accessing 48 bit instructions in legacy ISA encoding from external memory The external port performs three accesses to form one 4...

Page 230: ...an external data width of 16 bits External Port DMA Parameter Registers These registers are used to set up and control DMA through the proces sor s external port For information on these registers and...

Page 231: ...ss modifier ECEPx External Count External memory count read only alias of ICEPx CPEPx Chain Pointer Contains address of the next descriptor in internal memory Table 3 25 Enhanced DMA Parameter Registe...

Page 232: ...channel priority changes if using internal vs external index addresses The SHARC supports another internal to internal DMA module MTM which has higher priority by default but does only support standa...

Page 233: ...of the ICEP reg ister If ICEP is written the ECEP register is updated automatically Figure 3 21 Circular Buffered DMA Circular buffered DMA Figure 3 22 Figure 3 23 resembles the tradi tional core DAG...

Page 234: ...rnal port data direction for each individual TCB in a chain sequence Figure 3 22 Circular Buffering Write DMA Figure 3 23 Circular Buffering Read DMA 20 19 18 3 2 1 1 2 17 16 DESTINATION INDEX IIEP SO...

Page 235: ...ion pm seg_dmda EP TCB storage order CP EM EI C IM II var TCB1 6 0 M extbuffer N M buffer var TCB2 6 0 M extbuffer N M buffer section pm seg_pmco R0 0 dm CPEP0 R0 clear CPx register r0 DEN CHEN OFCEN...

Page 236: ...the DMA direction is external write TRAN 1 then it is a scatter DMA If TRAN 0 then it is a gather DMA This mode also supports chained and circular buffer chained DMAs External Address Calculation For...

Page 237: ...dded to the EIEP value to get the start address of the next block The external addresses are circular buffered if circular buffering is enabled Figure 3 26 Figure 3 27 Once the ICEP register for the f...

Page 238: ...re 3 24 Scatter DMA Writes 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 DESTINATION INDEX IIEP SOURCE INDEX EIEP DESTINATION BUFFER SOURCE BUFFER TAP LIST BUFFER OFFSET1 TAP LIST POINTER TPEP...

Page 239: ...ather DMA Reads 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 DESTINATION INDEX IIEP SOURCE INDEX EIEP SOURCE BASE EBEP DESTINATION BUFFER SOURCE BUFFER TAP LIST BUFFER OFFSET1 TAP LIST POINTE...

Page 240: ...A Writes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESTINATION INDEX IIEP SOURCE INDEX EIEP SOURCE BASE EBEP DESTINATION BUFFER SOURCE BUFFE...

Page 241: ...elay line DMA is described in the following sections The delay line DMA access consists of the following accesses in the order listed and is shown in Figure 3 28 on page 3 113 Note that in the figure...

Page 242: ...and the number of reads is determined by the RCEP register The write pointer in the EIEP register serves as the index address for these reads reads start from where writes end The EIEP register along...

Page 243: ...gle DMA sequence initialize the CPEP register to zero in the TCB For each 32 bit tap read the external read index is shown in Table 3 27 Note that one tap list entry starts multiple reads Figure 3 28...

Page 244: ...read address for tap N EIEP TL N 1 RMEP Second read address for tap N EIEP TL N 2 RMEP Third read address for tap N EIEP TL N RCEP RMEP Last read address for tap N EIEP TL N 1 First read address for...

Page 245: ...forming writes of the DMA data Prior to disabling any of these devices programs should check their respective status bits Internal Transfer Completion This mode of interrupt generation is enabled when...

Page 246: ...n both the write access and the delay line reads are completed In a chained delay line DMA the PCI bit determines if each delay line TCB generates an interrupt or not With scatter gather DMA the DMA c...

Page 247: ...ns on page 3 132 Table 3 29 Read Write Throughput Access1 1 Throughput for minimum wait states of 2 with no idle and hold cycles 8 Bit I O 16 Bit I O Write 32 bit word per 12 cycles 32 bit word per 6...

Page 248: ...6 32 bit words per transfer block For the analysis 16 bit DDR2 is used tFAW 10 tRRD 2 tRTP 2 tMRD 3 tRCD 3 tWTR 1 tRP 3 tRAS 8 CL 4 AL 4 tWR 4 Throughput is calculated by measuring time between the in...

Page 249: ...DRAM can be programmed to run at a number of different frequency ratios with respect to the core clock the fastest being half of the core clock or the same as the peripheral clock The core and SDRAM c...

Page 250: ...l specific After the AMI SDRAM DDR2 registers are configured the effect latency is 1 5 PCLK cycles minimum and 2 PCLK cycles maximum After the external port register is configured the effect latency i...

Page 251: ...ation of the external port DMA The following sections describe the programming steps for different types of DMA transfers Standard DMA Use the following procedure to set up and run a standard DMA on t...

Page 252: ...complete the new DMA descriptors are loaded and the process is repeated until CPEP 0x0 A DMA comple tion interrupt is generated at the end of each DMA block or at the end of entire chained DMA depend...

Page 253: ...rrupt is generated at the end of each DMA block or at the end of an entire chained DMA depending on the PCI bit setting Delay Line DMA 1 Configure the AMICTLx register with the desired wait states ena...

Page 254: ...e EXTS bit is 0 3 Write 0x0 to the ICEP and DMACx registers In cases where DMA is used without chaining writing to ICEP is not required 4 Re initialize the required DMA registers and enable the DMACx...

Page 255: ...th such a descriptor is programmed then the DMA might hang So a read count zero or a write count zero for a delay line DMA is also forbidden AMI Initialization After reset the SDCLK is running with th...

Page 256: ...in the PMCTL register 2 Wait at least 15 core clock cycles until the new SDCLK frequency has been settled up correctly 3 Assign external banks to SDC in the EPCTL register 4 Wait at least 8 core clock...

Page 257: ...the PLL divider by setting the PLLDx bits bits 6 7 in the PMCTL register 3 Select the clock divider CCLK to SDRAM ratio by setting the ratio bits PMCTL register 4 Wait 15 CCLK cycles During this time...

Page 258: ...on and causes a performance degradation for the other specifications The reduction of the system clock violates the minimum specifications while increasing the system clock violates the maximum tREF s...

Page 259: ...initial ize the SDC and the SDRAM to the new frequency The SDRAM device is now ready to be accessed DDR2 Controller The following sections are specific to DDR2 SDRAM memory on the ADSP 2146x processo...

Page 260: ...DDR2CTL5 3 registers 11 Enable DDR size row column bank in the DDR2CTL0 register 12 Start the power up sequence with the DDR2PSS bit Wait for DLL external bank calibration The device now ready for an...

Page 261: ...ged stable new clocks must be provided to DRAM before the precharge power down may be exited 5 Reset the on chip DLL and wait until it locks to new frequency 6 Depending on new the clock frequency an...

Page 262: ...he bus width setting X16DE bit 1 Assign external bank 0 to SDRAM in the EPCTL register default 2 Wait at least 8 CCLK cycles effect latency 3 Configure the SDCTL and SDRRC registers accordingly Extern...

Page 263: ...ernal memory and two instructions when executing from external memory 6 When a new external memory instruction fetch occurs on the pro cessor due to a jump from internal to external memory or after a...

Page 264: ...Programming Models 3 134 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 265: ...well as co processing and multiprocessing schemes The port specifications are shown in Table 4 1 Table 4 1 Link Port Specifications Feature Link Port1 0 Connectivity Multiplexed Pinout No SRU DAI Requ...

Page 266: ...166 MHz or peripheral clock frequency PCLK CCLK 2 which ever is lower indepen dent of the programmed ratio The link ports contain the features shown in the following list Operate independently and si...

Page 267: ...the ADSP 2146x data sheet Register Overview Each link port has its own control and status register These are described in the following sections and in Link Port Registers on page A 63 For information...

Page 268: ...in Figure 4 2 consists of eight data lines LDATx7 0 x 0 1 a link port clock line LCLKx and a link port acknowledge line LACKx The LCLKx and LACKx pins of each link port allow handshaking for asynchro...

Page 269: ...s LACKx when it is ready to accept another word in the receive buffer RXLBx The transmitter samples LACKx driven by the receiver at the begin ning of each word transmission that is after every 4 bytes...

Page 270: ...dless of the state of LACKx The following list describes the stages shown in Figure 4 3 1 LCLK stays high at byte 0 if LACK is sampled low on the previous LCLK rising edge LCLK high indicates a stall...

Page 271: ...buffer on the falling edge of LCLKx The receive operation is purely asynchronous and can occur at any frequency up to 166 MHz or peripheral clock frequency which ever is less When a link port is not...

Page 272: ...l pull down and an external pull down 20K Ohms is requ ried on the LACKx and LCLKx signals Figure 4 4 Figure 4 5 and Figure 4 6 show various timings for the link port Figure 4 4 Enable Transmitter and...

Page 273: ...CLKx FALLING EDGE LDAT7 0 DRIVEN BY TRANSMITTER LCLKx DRIVEN BY TRANSMITTER TRANSMITTER SAMPLES LACKx HERE TO DECIDE WHETHER TO TRANSMIT NEXT WORD BYTE 3 MSB BYTE 0 LSB LACKx MAY DEASSERT AFTER BYTE 0...

Page 274: ...re flag that passes between processors At reset the token is set to reside in the link port of one device making it the mas ter and the transmitter When a receiver slave wants to become the master it...

Page 275: ...nows through software protocol whether it is supposed to respond with actual data or whether it is being asked for the token The token release word can be any user defined value Since both the transmi...

Page 276: ...OR CORE Rx TO ACCEPT DMA SIZE SET UP LINK PORT FOR Rx DMA AND DMA COMPLETE IRQ DMA TRANSFER COMPLETE SET UP LINK PORT FOR CORE Rx DMA TRANSFER COMPLETE LINK PORT CORE Rx ENABLED READ RECEIVE BUFFER TE...

Page 277: ...bits is to be used it is important to note the following If a link port that is configured to receive is disabled while LACKx is asserted there is an RC delay before the external pulldown resistor on...

Page 278: ...omes empty the LCLKx signal is deasserted Receive Buffer In the receive buffer data is transferred to the core or DMA from the buf fer whereas the shift register performs the packing least significant...

Page 279: ...or core may read or write link buffers directly using the full or empty status bit of the link buffer to automati cally pace the operation The full or empty status of a particular link buffer can be d...

Page 280: ...fore the link port control register is configured After setting the DMA enable bit the transfer starts until the word count reaches zero the DMA has finished Interrupts The following sections and Tabl...

Page 281: ...request interrupt is generated Now the receiver can initiate the transfer 4 A link port invalid transmit LPIT is generated if the transmitter is driving LCLKx high because the receiver has not assert...

Page 282: ...enabled the DMA engine checks if DMA has been completed If CLBx is zero and chaining is enabled the DMA engine also checks if CPLBx also is zero Internal Transfer Completion This interrupt performs l...

Page 283: ...xt course of action Chained DMA In chained DMA operations the processor automatically sets up another DMA transfer when the current DMA operation completes The chain pointer register points to the nex...

Page 284: ...ll it For the receiver programs need to perform two reads from the receive buffer to empty it Then the next interrupt occurs when the buffer becomes not full or not empty again Two reads and or writes...

Page 285: ...quest The link service request status of the port is set whenever the port is not enable and one of LxACK or LxCLK is asserted high If link service requests are in use they should be masked out when t...

Page 286: ...is returned Writing to a full trans mit buffer with the BHD bit set overwrites the existing data Effect Latency The total effect latency is a combination of the write effect latency core access plus...

Page 287: ...divider by setting the PLLDx bits bits 6 7 in the PMCTL register 3 Select the link port clock divider CCLK to LPCLK ratio by setting the LPCKRx bits bits 21 and 22 in the PMCTL register 4 Enable the n...

Page 288: ...k port for receive LTRAN 0 2 The processor enables the link port by setting the LEN bit DMA is enabled by setting the LDEN bit in the LCTLx register 3 The external device begins writing data to the RX...

Page 289: ...e this is a transmit setting LDEN automatically asserts an internal DMA request 3 After the request is granted the internal DMA transfer is performed filling the TXLBx buffer s FIFO 4 The external dev...

Page 290: ...Programming Model 4 26 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 291: ...nnectivity Multiplexed Pinout No SRU DAI Required No SRU DAI Default Routing N A SRU2 DPI Required No SRU2 DPI Default Routing N A Interrupt Control Yes Protocol Master Capable Yes Slave Capable No Tr...

Page 292: ...her internal to internal DMA module external port which does support multiples DMA modes Register Overview MTM control register MTMCTL Enables the read and write DMA channels across the internal memor...

Page 293: ...ng 64 bit bursts of data between internal memories The MTM controller supports data in normal word address space only 32 bit External to external DMA transfers are not supported Data Transfer Types Th...

Page 294: ...memory location to another This register also allows verification of current DMA status during writes and reads Interrupts There are two DMA channels one write channel and one read channel When the tr...

Page 295: ...rite effect latency see the SHARC Processor Programming Reference MTM Effect Latency After the MTM register is configured the effect latency is 1 5 PCLK cycles minimum and 2 PCLK cycles maximum Progra...

Page 296: ...Programming Model 5 6 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 297: ...needed To meet this need the ADSP 214xx SHARC processors off load some of the most frequently used and intensive processing into hardware accelera tors An accelerator dedicated for filter processing c...

Page 298: ...g N A SRU2 DPI Required No SRU2 DPI Default Routing N A Interrupt Control Yes Protocol Master Capable N A Slave Capable N A Transmission Simplex N A Transmission Half Duplex N A Transmission Full Dupl...

Page 299: ...e is designed to connect to the processor s DMA engine acting like a peripheral and implements a synchronous pipeline read write protocol with a pipeline depth of 1 Figure 6 1 FFT Block Diagram CORE P...

Page 300: ...oating point adders Has a control unit with configuration registers responsible for all memory addresses and strobe generation Contains a 8 x 32 deep input output FIFO unit Register Descriptions The a...

Page 301: ...eripheral clock fPCLK Functional Description The FFT accelerator is comprised of a compute block data memory and coefficient memory The design allows programs to offload an FFT calcu lation by initial...

Page 302: ...or has a 512 location deep 32 bit wide twiddle memory organized into two independent blocks 256x2 It allows fetching real and imaginary twiddles simultaneously Accelerator States The FFT accelerator h...

Page 303: ...ssive FFT calculations the coefficient need not be read again only the next set of data has to be read When a specified number of data words are read the state automati cally moves to processing Proce...

Page 304: ...d data is selected this is the required input format or output for mat Programs can optionally select the input or output data streams to be unpacked In this mode the first samples are all real follow...

Page 305: ...tical Coeff Buffer 2 V Horizontal Coeff Buffer 2 H Special Coeff Buffer 4 N Twiddles For N 256 the FFT accelerator follows the Divide and Conquer approach Therefore three types of coefficient buffers...

Page 306: ...SP_CF N 1 Im SP_CF N 1 Im SP_CF N 1 Re SP_CF N 1 4N words Where Re CF x Real part of the complex coefficient CF x Im CF x Imaginary part of the complex coefficient CF x Re SP_CF x Real part of specia...

Page 307: ...mory and the next FFT can start Large FFT Computation 512 Points For large FFTs NOVER256 non zero the model looks different since the twiddle data do not fit completely into the local memories The FFT...

Page 308: ...t buffer 1024 modifier 2H circbuf 2N 3 FFT computation 4 Output DMA to special buffer 1024 Special Product Number of Iterations is N 128 4 1 First iteration a Input coeff DMA from special coeff buffer...

Page 309: ...m special coeff buffer 512 offset 1536 b Input DMA from special buffer 256 offset 768 c FFT computation d Output DMA to special buffer 256 offset 768 Horizontal FFT 1 Input coeff DMA from horizontal c...

Page 310: ...te then the write state to read the results back into internal memory The accelerator then moves automati cally back into the read state for the next FFT frame In this state multiple linked TCBs which...

Page 311: ...A and therefore does not require core intervention This allows the core to perform other sys tem tasks The core is used to configure the DMA parameter registers and the accelerator control registers a...

Page 312: ...er chain pointer DMA The input TCB structure consists of index modify count and chain pointer register values for input data The input TCB also consists of length and base pointer register values to s...

Page 313: ...gister values for twiddles load DMA parameter register values for output data Intermediate results for large FFT are stored in the internal memory The circular access type is used for large FFTs to pr...

Page 314: ...he respective chain pointer registers When a DMA interrupt occurs programs can find whether the input DMA interrupt occurred or the output DMA interrupt occurred by reading the DMA status register FFT...

Page 315: ...is section V Number of rows H Number of columns N V H Reads from internal memory take 2 cycles word Writes to internal memory take 1 cycle word It takes 2 PCLK cycles to compute a single complex butte...

Page 316: ...tures The following sections describe the debugging features available on the accelerator Local Memory Access Setting the FFT_DBG bit in the FFTCTL1 register puts the accelerator into debug mode and a...

Page 317: ...ffect latency of two PCLK cycles Wait for at least four CCLK cycles after selecting an accelerator before accessing any of its registers Programming Model There are two separate programming models one...

Page 318: ...bit words and wait until the DMA is complete or chain DMA in Step 4 This step is not needed if twiddles are already in the coefficient memory of the accelerator 6 Configure a data DMA to read N comple...

Page 319: ...the FFT_RST bit in the FFTCTL1 register and wait for a min imum of 4 CCLK cycles 4 Program the FFTCTL1 register with FFT_RST 0 FFT_EN 1 FFT_START 1 FFT_DMAEN 1 FFT_DEBUG 0 5 Configure a coefficient D...

Page 320: ...de waiting for next batch of FFTs N 512 No Repeat For details on the storage format of the coefficients see Internal Memory Storage on page 6 8 Configure the FFT Control Register 1 Configure the ACCSE...

Page 321: ...ut is always expected to be in alternate real and imaginary format and the output is always generated in the same format 8 Configure a data receive DMA to read 2N data points from the accelerator into...

Page 322: ...acceler ator into the output buffer with a modify value 2V and a circular buffer length of 2N 1 There is no need to wait until the DMA in Step 9 completes Chain a data DMA of count 1 that reads the la...

Page 323: ...g Mode The next sections show the steps required for reading and writing local memory in debug mode Write to Local Memory 1 Enable the FFT module using the PMCTL1 register 2 Wait at least 4 CCLK cycle...

Page 324: ...egister FIR Accelerator Finite Impulse Response FIR filters are used in a wide array of applica tions and can be used in multi rate processing in conjunction with an interpolator or decimator Features...

Page 325: ...such as filter TAP length window size sample rate conversion up down sampling and ratio DMA Status Register FIRDMASTAT Provides the status of the FIR accelerator operation This information includes ch...

Page 326: ...the peripheral clock frequency PCLK The FIR accelerator has following logical sub blocks 1 A data path unit that consists of a A 1024 deep coefficient memory b A 1024 deep delay line for the data Figu...

Page 327: ...g the DMA filter configuration reg isters and reading the status register 4 DMA bus interface for transferring data and or coefficients to and from the accelerator 5 DMA configuration registers includ...

Page 328: ...MAC result is written to the internal memory s output buffer If the same channel is requested again the partial result register is updated with the intermediate MAC result via DMA from the internal me...

Page 329: ...into coefficient memory Four coefficients can be fetched from the coeffi cient memory simultaneously If the soft filter length is more than 1024 processing is done in multi iteration mode Prefetch Dat...

Page 330: ...ltering Flow Load chain pointer and control registers and enable accelerator Load coefficients for Perform all MACS and calculate result END NO NO YES the iteration Prefill delay line DMA partial sum...

Page 331: ...filter for example this procedure is done N 4 times 3 When all the TAPs complete the accelerator adds the four MAC outputs together to the previous partial sum if any to calculate the final result 4...

Page 332: ...Assuming M decimation ratio the total size of the input buffer should at least be equal to N 1 WxM If the input buffer that needs to be processed is x n x n 1 x n 2 x n WxM 1 it should be stored in t...

Page 333: ...re N is the number of filter coefficients c i i 0 N 1 are the fil ter coefficients and x n represents the input time series Single Iteration Results are computed in single iteration when the soft filt...

Page 334: ...next channel A configu rable window size parameter is provided to specify the length of the window Multi Rate Processing Multi rate filters change the sampling rate of a signal they convert the input...

Page 335: ...the interpolation ratio Note that the output rate is L times the input rate In this mode according to the ratio specified in configuration register FIR logic inserts L 1 zeros between any two input sa...

Page 336: ...the corresponding TCB is loaded from internal memory 1 The FIRCTL2 value is fetched from internal memory and is used to configure the filter parameters for that channel 2 The accelerator fetches the...

Page 337: ...terations are done to process the window Figure 6 6 Single Channel Filtering Flow Load I M B L registers for coefficient and data I O Load coefficients into Compute result and store in internal memory...

Page 338: ...e first word is the LSW the 2nd the MSW and the third word is a 16 bit overflow the remain ing 16 bits are padded with zeros Therefore for fixed point WINDOWSIZE WINDOWSIZE 3 If signed fractional form...

Page 339: ...in FIR Accelerator TCB on page 2 16 and Figure 6 7 the accelerator loads the TCB into its internal registers and uses these values to fetch coefficients and data and to store results After processing...

Page 340: ...interrupts to the peripheral interrupt inputs of the core One interrupt line is shared by all the DMA interrupts and the other by MAC status interrupts Separate status registers are provided to furth...

Page 341: ...gister FIRMACSTAT on page A 83 Service Channel Interrupts Based on the FIR_CCINTR bit in the FIRCTL1 register both bits FIR_DMAWDONE or FIR_DMAACDONE are set in the FIRDMSTAT register if either of the...

Page 342: ...annot cross the data memory coefficient memory boundary Single Step Mode Programs can single step through the MAC operations and observe the memory contents after each step The FIR_DBGMODE FIR_HLD and...

Page 343: ...s Read through put from memory throughput is one 32 bit data word per two peripheral clock cycles The following information describes the performance of the FIR accelera tor in processor cycles Total...

Page 344: ...the maxi mum processing time is 10 s The computation of the filter requires TCB load 4 N W N 4 2 C For window size 1 49 4 512 1 512 4 2 2227 PCLK 9 8 us For window size 10 49 4 512 10 512 4 2 3397 PCL...

Page 345: ...anation provided in Coefficients and Input Buffer Storage on page 6 35 4 The core configures the FIRCTL1 register with the number of chan nels one channel fixed or floating point format 5 Set the enab...

Page 346: ...coefficient memory and loads the FIRCTL2 register to configure the filter parameters correspond ing to that channel The accelerator then calculates output samples corresponding to one Window and stor...

Page 347: ...s Figure 6 8 Wait for Core Intervention Idle if CAI bit 0 Core sets up control register and initiates RUN command Load TCB for current channel Process one window of current channel All channels done A...

Page 348: ...UGCTL register 5 Set the FIR_ADRINC bit in FIRDEBUGCTL register for address auto increment 6 Write start address to the FIRDBGADDR register Note if bit 11 is set coefficient memory is selected 7 Wait...

Page 349: ...ingle step each iteration is updated in the emulator session FIR Programming Example An application needs FIR filtering of six channels of data The first four channels require 256 TAP filtering and th...

Page 350: ...corresponding channel s data buffer coefficient buffer and output data buffer The location of the first channel s TCB is writ ten to the CPFIR register The FIRCTL1 register is then programmed with an...

Page 351: ...IR supports IEEE floating point format 32 40 bit Sample based or window based processing Up to 12 cascaded biquads per channel Up to 24 filter channels available Register Overview The following sectio...

Page 352: ...he status of the MAC operations Debug Mode Control IIRDEBUGCTL Controls the debug mode operation of the accelerator Clocking The IIR accelerator runs at the maximum speed of the peripheral clock fPCLK...

Page 353: ...uad structure Figure 6 9 IIR Accelerator Block Diagram BIQUAD BIQUAD CORE PMD DMD BUS IOD0 BUS BIQUAD COMPUTE UNIT 1 MAC RESULT REGISTER COEFF ACCESS CONTROL DATA AND STATE ACCESS CONTROL C O E F F I...

Page 354: ...tiplier and adder MAC unit An input data buffer to efficiently supply data to MAC One 40 bit result register to hold result of biquad Configuration registers for controlling various parameters such as...

Page 355: ...Unit The MAC unit shown in Figure 6 11 has a pipelined multiplier and accu mulator unit that operates on the data and coefficient fetched from the data and coefficient memory The MAC can perform eithe...

Page 356: ...of all the biquads At start up DMA loads the coefficients from internal memory into coefficient memory Internal Memory Storage This section describes the required storage model for the IIR accelerator...

Page 357: ...mple is calculated In window based mode multiple output samples up to 1024 equal to the window size of that channel are calculated After these calculations are complete the accelerator begins processi...

Page 358: ...lication Data Transfers The IIR filter works exclusively through DMA DMA Access The IIR accelerator has two DMA channels accelerator input and output to connect to the internal memory The DMA controll...

Page 359: ...s and uses these values to fetch coefficients and data and to store results After processing a win dow of data for any channel the accelerator writes back the IIRII input index register and IIROI outp...

Page 360: ...s registers are provided to further differentiate the various sources Interrupt Sources There are two interrupt sources associated with the accelerator The IIR_CCINTR bit in the IIRCTL1 register contr...

Page 361: ...status interrupt is generated whenever a floating point operation results in an arithmetic exception Reading the IIRMACSTAT register returns for which MAC unit is causing an exception Debug Features T...

Page 362: ...crement bit IIR_ADRINC is set the address register auto increments on IIRDBGWRDATA_H L writes and IIRDBGRDDATA_H L reads During auto increment the IIR_DBGADDR register cannot cross the data memory coe...

Page 363: ...ecting another accelerator before accessing any of its registers IIR Throughput Data throughput is one 32 bit data word per peripheral clock cycle for writes to memory provided there are no conflicts...

Page 364: ...channel The total number of channels is configured using the IIRCTL1 register and DMA is enabled The procedure that the accelerator uses to process biquads is shown in Figure 6 14 and described in the...

Page 365: ...RCTL1 register 4 Set the IIR_DBGMODE IIR_DBGMEM and IIR_HLD bits in the IIRDE BUGCTL register Figure 6 14 Biquad Processing Program Flow Preload all the coefficients and initialize intermediate result...

Page 366: ...register Reading from Local Memory 1 Enable IIR module in PMCTL1 register 2 Wait at least 4 CCLK cycles 3 Clear the IIR_DMAEN bit in the IIRCTL1 register 4 Set the IIR_DBGMODE IIR_DBGMEM and IIR_HLD...

Page 367: ...and channel 2 has eight biquads The win dow size for all channels is 32 1 Create a circular buffer in internal memory for each channel s data The buffer should be large enough to avoid overwriting dat...

Page 368: ...ll the 8 biquads b Once all the coefficients and Dk values are loaded the con troller loads the TCB of first channel and fetches the input sample It then starts calculating the first biquad of the fir...

Page 369: ...ns to power control and conversion The interface specifications are shown in Table 7 1 Table 7 1 PWM Specifications Feature Availability Connectivity Multiplexed Pinout Yes External port SRU DAI Requi...

Page 370: ...nized to each other Complementary outputs allows bridge based applications A block diagram of the module is shown in Figure 7 1 The generation of the four output PWM signals on pins AH to BL is contro...

Page 371: ...h side or the low side output In addition the output control unit allows individual enabling disabling of each of the four PWM output signals The PWM interrupt controller generates an interrupt at the...

Page 372: ...ing on page 23 28 Table 7 2 PWM Pin Descriptions Multiplexed Pin Name Direction Description PWM_AH3 0 O PWM output of pair A produce high side drive signals PWM_AL3 0 O PWM output of pair A produce lo...

Page 373: ...ters Reference PWM global control register PWMGCTL Enables or disables the four PWM groups simultaneously in any combination for syn chronization between the PWM groups PWM global status register PWMG...

Page 374: ...in Figure 7 1 are described in detail in the following sections Two Phase PWM Generator Each PWM group is able to generate complementary signals on two out puts in paired mode or each group can provi...

Page 375: ...M switching fre quency of PWMPERIOD values of 0 and 1 are not defined and should not be used when the PWM outputs or PWM sync is enabled Duty Cycles The two 16 bit read write duty cycle registers PWMA...

Page 376: ...ated register and can be converted to time by simply multiplying by the fundamental time increment PCLK and comparing this to the two s com plement counter Note that the switching patterns are perfec...

Page 377: ...it and illustrated in Figure 7 2 may be written as The range of TAH is and the corresponding duty cycles are Figure 7 2 Center Aligned Paired PWM in Single Update Mode Low Polarity PWMPERIOD PWMPERIOD...

Page 378: ...are all changed in the sec ond half of the PWM period The same value for any or all of these quantities can be used in both halves of the PWM cycle However there is no guarantee that a symmetrical PW...

Page 379: ...e The corresponding duty cycles are Figure 7 3 Center Aligned Paired PWM in Double Update Mode Low Polarity T AH PWMPERIOD 1 2 PWMPERIOD 2 2 PWMCHA 1 PWMCHA 2 PWMDT 1 PWMDT 2 tPCLK PWMTM1 PWMTM2 PWMCH...

Page 380: ...nd turn ing on the complementary signal AL This short time delay is introduced to permit the power switch being turned off AH in this case to completely recover its blocking capability before the comp...

Page 381: ...it of the PWMSEG register is set 1 then the correspond ing PWM output is disabled regardless of the value of the corresponding duty cycle register This PWM output signal remains disabled as long as th...

Page 382: ...high side PWM signal from the timing unit for example AH is diverted to the associated low side output of the output control unit so that the signal ultimately appears at the AL pin The corresponding...

Page 383: ...e explained in more detail below Full On The PWM for any pair of PWM signals operates in full on when the desired high side output of the two phase timing unit is in the on state low between successiv...

Page 384: ...signal is allowed to turn on provided the desired output is still scheduled to be in the on state after the emergency dead time delay Figure 7 4 illustrates two examples of such transitions In a when...

Page 385: ...Enable Figure 7 4 Normal Modulation to Full ON to Full OFF Transition PWMPERIOD PWMPERIOD PWMPERIOD1 2 0 PWMPERIOD1 2 PWMTM2 2 PWM_AH PWM_AL PWM_AH PWM_AL FULL OFF FULL ON 2xPWMDT PWMCHA1 EMERGENCY DE...

Page 386: ...zero programmed through the PWMAx registers produces a PWM waveform with 50 duty cycle For even values of period the PWM pulse width is exactly period 2 whereas for odd values of period it is equal t...

Page 387: ...there are several options to choose from Center Aligned Single Update Mode Duty cycle values are programma ble only once per PWM period so that the resultant PWM patterns are symmetrical about the mi...

Page 388: ...as its own set of registers which control the operation of that group The operating mode of the PWM block single or double update mode is selected by the PWM_UPDATE bit bit 2 in the PWM control PWMCTR...

Page 389: ...his point the count direction changes and the timer continues to increment from 0 to the PWMPERIOD 2 value Also shown in Figure 7 7 are the PWM interrupt pulses for operation in edge aligned mode An P...

Page 390: ...n effect this means that the characteristics and resultant duty cycles of the PWM signals can be updated only once per PWM period at the start of each cycle The result is that PWM patterns that are sy...

Page 391: ...ond half of each PWM period This status bit allows programs to make a determination of the particular half cycle during implementation of the PWM interrupt service routine if required The advantage of...

Page 392: ...ynchronization of PWM Groups The PWMGCTL register enables or disables the four PWM groups in any combination This provides synchronization across the four PWM groups The PWM_SYNC_ENx bits in this regi...

Page 393: ...The PWM inter rupt can trigger the ADC to sample data for use during the ISR During processor boot the PWM is initialized and program flow enters a wait loop When a PWM interrupt occurs the ADC sample...

Page 394: ...enever a period starts the PWM interrupt is generated The interrupt latch bit is set 1 PCLK cycle after the PWM counter resumes Since all four PWM units share the same interrupt vector the interrupt s...

Page 395: ...g aid Each register is available per unit The registers return current status information about the AH AL BH BL output pins Emulation Considerations An emulation halt does not stop the PWM period coun...

Page 396: ...Effect Latency 7 28 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 397: ...The media local bus topology sup ports communication among the MLB controller and MLB devices where the MLB controller is the interface between the MLB devices and the MOST network More information o...

Page 398: ...n MediaLB and on chip memory with single word core driven transfers or with DMA block transfers The MLB interface on supports MOST25 and MOST50 data rates Isochronous modes of transfer are not support...

Page 399: ...direction transmit and receive DMA and core driven data transport methods Memory for channel data buffering System channel command handling Hardware loop back test mode support Support for transmit co...

Page 400: ...us Register MLB_SSCR System Data Configura tion Register MLB_SDCR System Mask Configuration Register MLB_SMCR Controls system features of the MediaLB interface and system interrupt handling Synchronou...

Page 401: ...Configuration Registers MLB_LCBCRx These registers allow programs to control and monitor the buffers used in the MLB network Clocking Media Local Bus Clock This clock is generated by the MLB controll...

Page 402: ...currently being transmitted for example synchronous asynchronous or control The MLB device receiving the channel data outputs a status byte RxSta tus on the MLBSIG line immediately after the transmit...

Page 403: ...register When enabled the synchronous logical channel begins transmitting data only at a MediaLB frame boundary A maskable interrupt is generated when the loss of frame synchronization occurs In order...

Page 404: ...er of data between MLB and internal memory All hardware channels must use the same data transfer method Mixed mode operation where hardware channels operate in both I O mode and DMA mode is not suppor...

Page 405: ...I O service request to system software I O service requests are generated when The number of valid qualdets in the local channel buffer falls below the threshold for transmit channels or valid quadlet...

Page 406: ...l channels Each channel can address up to 16k words The DMA address is comprised of A 5 bit base configured in the MLB base register set MLB_SBCR MLB_IBCR MLB_ABCR or MLB_CBCR for the corresponding ch...

Page 407: ...operate in ping pong DMA mode when the channel mode select bits MLB_CECRx register bits 25 26 00 When MLB is con figured in ping pong mode the MLB_CCBCRx and MLB_CNBCRx registers are used to configur...

Page 408: ...e MLB_CCBCRn register cleared the local channel RDY bit and is available to accept the next buffer Software may then pre pare the next buffer by writing BSA BEA and RDY bits During the processing of t...

Page 409: ...ar buffer Set the RDY bit in the MLB_CSCRx register to initiate buffer processing At the start of buffer processing the beginning address of the circu lar buffer BSA is loaded into BCA field of the ML...

Page 410: ...Table 8 2 Overview of MLB Interrupts Interrupt Source Interrupt Condition Interrupt Completion Interrupt Acknowledge Default IVT MLB 31channels System Status Interrupts System Detects Channel Scan Net...

Page 411: ...bits 16 23 in the MLB_CECRx register The channel interrupt status register MLB_CICR reflects the interrupt sta tus of the individual logical channels For example if an interrupt is pending in logical...

Page 412: ...nnel N 1 where N 0 2 4 30 Programming Model The following sections provide procedures that are helpful when program ming media local bus interface I O Interrupt Mode To configure the MLB interface for...

Page 413: ...ffer has data to be read Within the ISR check if this status bit is set If set read the data from the receive data buffer MLB_CCBCRx 8 Clear all interrupts by writing 0x0000FFFF to the MLB_CSCRx regis...

Page 414: ...ster for ping pong or circular buffer DMA mode transfer direction chan nel type channel address and also to generate appropriate interrupts 9 Configure the MLB_CNBCRx register with the buffer start an...

Page 415: ...based on a set of configura tion registers This allows the peripherals to be interconnected to suit a wide variety of systems It also allows the SHARC processors to include an arbitrary number and va...

Page 416: ...s refer to I O Pin Buffers on page 9 7 The DAI DPI may be used to connect combinations of inputs to combi nations of outputs This function is performed by the SRU SRU2 via memory mapped control regist...

Page 417: ...utes physical pins connected to a bonded pad Miscellaneous Signal Routing Registers SRU_MISCx Associated with group E allows programs to route to the DAI interrupt latch PBEN input routing or input si...

Page 418: ...rs on page A 218 Clocking The fundamental timing clock of the DAI DPI modules is peripheral clock 2 PCLK 2 Functional Description Figure 9 1 shows how the DAI pin buffers are connected via the SRU Thi...

Page 419: ...tation the SRU and DAI would show several types of data being routed from several sources including the following Serial ports SPORT Precision clock generators PCG Input data port IDP Asynchronous sam...

Page 420: ...cision clock generator units C D can be assigned to access DAI and or DPI pins Figure 9 1 DAI DPI Functional Block Diagram SRU SRU2 DAI DPI PIN BUFFER PERIPHERAL A PERIPHERAL B PERIPHERAL C MISCELLANE...

Page 421: ...rts or if the peripheral has more than one signal that performs this function for example IDP channels The mnemonic always ends with _I if the signal is an input or with _O if the signal is an output...

Page 422: ...is logic high and turning it off when its value is logic low When the pin enable is asserted the pin output is logically equal to pin input and the pin is driven When the pin enable is deasserted the...

Page 423: ...at system startup by tying the pin buffer enable to a fixed value either logic high or logic low is often the simplest and cleanest way to configure the SRU When the DAI pin is to be used only as an o...

Page 424: ...is not used Although not strictly necessary it is recommended programming practice to tie the pin buffer input to logic low whenever the pin buffer enable is tied to logic low Figure 9 5 and Figure 9...

Page 425: ...the pin is depending on the bus activities If PBEN high the driver is conducting input always low level and ties the bus low level Note that for the SPI the ODP bit in the SPICTL register must be ena...

Page 426: ...Buffers The miscellaneous buffers Figure 9 7 are used to interconnect signals from different routing groups These buffers have the following characteristics 1 Only for internal connections no pin buf...

Page 427: ...and Table 9 3 provide routing options for the DAI and DPI miscellaneous buffers Note that while the Interrupt and Miscellaneous Inputs have different naming conventions they are the same physical inp...

Page 428: ...flow in a pin buffer from an external perspective for example when a serial port SPORT is completely routed off chip it uses four pins clock frame sync data channel A and data channel B Because all fo...

Page 429: ...are automatically driven If operating in slave mode the SPORTx_CLK_O and SPORTx_CLK_PBEN signals are automatically disabled and the SPORTx_CLK_I signal expects an external clock The input and output s...

Page 430: ...ires a static high from the SRU In order to disable the pin buffer output software must clear the pin buffer enable input accordingly Signal Routing Units SRUs The following sections provide more deta...

Page 431: ...l of the inputs and outputs of the DAI peripherals a number of additional signals from the core and all of the connections to the DAI pins The SRU2 for DPI contains three groups that are named sequent...

Page 432: ...tible inputs These connections are implemented as a set of memory mapped registers with a bit field for each input The outputs are implemented as a set of bit encodings Conceptually a patch cord is us...

Page 433: ...OGIC LOW 0 LOGIC HIGH 1 DAI_PB01_O DAI_PB02_O DAI_PB03_O DAI_PB04_O DAI_PB05_O DAI_PB06_O DAI_PB07_O DAI_PB08_O DAI_PB09_O DAI_PB10_O DAI_PB12_O DAI_PB13_O DAI_PB14_O DAI_PB15_O DAI_PB16_O DAI_PB17_O...

Page 434: ...ns In this section three types of SRU routing are demonstrated 1 Listing 9 1 and Figure 9 10 show the SRU connection between the DAI and pin buffers 2 Listing 9 2 on page 9 22 and Figure 9 11 on page...

Page 435: ...el low nop SRU DAI_PB14_O DAI_PB03_I connect DAI pin 14 to DAI pin 3 nop SRU DAI_PB14_O DAI_INT_22_I connect DAI pin 14 to DAI interrupt 22 Figure 9 10 SRU Connection Between DAI Pin Buffers SRU PBEN0...

Page 436: ...output nop SRU SPORT0_CLK_O DAI_PB03_I connect to DAI pin 3 nop SRU SPORT0_CLK_O SPORT1_CLK_I connect to SPORT1 nop SRU SPORT0_CLK_O SPORT2_CLK_I connect to SPORT2 Figure 9 11 SRU Connection Between D...

Page 437: ...14 nop SRU PCG_CLKB_O DAI_PB14_I connect PCG and pin 14 nop SRU SPORT2_FS_O MISCA4_I connect SPORT to MISCA nop SRU MISCA4_O PBEN14_I connect MISCA to PBEN14 nop SRU HIGH INV_MISCA4_I invert MISCA4 in...

Page 438: ...Rx clock TDM clock DAI Pin Buffer20 1 Logic level high Logic level low B Data SPORT7 0 A B SRC3 0 data TDM data IDP7 0 S PDIF Tx Rx SPORT7 0 A B SRC3 0 data TDM data S PDIF Tx Rx C Frame Sync SPORT7 0...

Page 439: ...T7 0 AB data PCG A B clk FS DAI Pin Buffer 8 1 SR_CLK SR_LAT SR_SDI Table 9 5 DPI Routing Capabilities DPI Group Input xxxx_I Output xxxx_O A Miscellaneous Signals SPI MOSI MISO DS CLK SPIB MOSI MISO...

Page 440: ...purpose input output GPIO pins Each of the DAI pins can also be set to drive a high or low logic level to assert signals They can also be used as DAI DPI interrupt sources On the DAI two dedicated inp...

Page 441: ...ther than the pin buffer enable signal which is generated by the peripheral may be routed to the pin buffer enable input For example an outside source may be used to gate a pin buffer output by contro...

Page 442: ...vert the input level on the buffer by a bit setting The SRU enables many possible functional changes both within the pro cessor as well as externally Used creatively it allows system designers to radi...

Page 443: ...A_O PBEN_O DAI Pin03 SPORT0_DB_I SPORT0_DB_O PBEN_O DAI Pin04 DAI Pin05 DAI Pin06 SPORT1_DA_I SPORT1_DA_O PBEN_O DAI Pin07 SPORT1_DB_I SPORT1_DB_O PBEN_O DAI Pin08 SPORT0_FS_I SPORT0_FS_O PBEN_O SPORT...

Page 444: ...SPORT3_DA_I SPORT3_DA_O PBEN_O DAI Pin11 SPORT3_DB_I SPORT3_DB_O PBEN_O DAI Pin12 SPORT2_CLK_I SPORT2_CLK_O PBEN_O SPORT2_FS_I SPORT2_FS_O PBEN_O DAI Pin15 DAI Pin16 SPORT4_DA_I SPORT4_DA_O PBEN_O SPO...

Page 445: ...SPI control register settings to configure master or slave operation Figure 9 15 DPI Default Routing PBEN_O SPI_CLK_I SPI_CLK_O PBEN_O DPI Pin03 SPIDS_I DPI Pin04 SPI_MOSI_I SPI_MOSI_O PBEN_O DPI Pin0...

Page 446: ...This change of output and the resulting behavior causing the sound to be muted results in an alert signal an interrupt being introduced in response if the detection of a protocol change is a high pri...

Page 447: ...events generally occur infrequently relative to the SHARC processor core the DAI interrupt controller reduces all of its interrupts onto two inter rupt signals within the core s primary interrupt syst...

Page 448: ...e low priority it is latched in the DAI_IMASK_L register Similarly when any bit in the DAI_IMASK_L register is set 1 bit 6 in the LIRPTL register is also set and the core services that interrupt with...

Page 449: ...e DAI interrupts trigger an interrupt in the core and the interrupt latch is set A read of this bit does not reset it to zero The bit is only set to zero when the cause of the interrupt is cleared A D...

Page 450: ...rm Table 9 7 provides an overview of DPI miscellaneous interrupts DAI DPI Interrupt Mask Events For interrupt sources that correspond to waveforms as opposed to DAI event signals such as DMA complete...

Page 451: ...dge Latch on the falling edge Latch on both the rising and falling edge Table 9 8 shows which interrupts are valid on rising and or falling edges Use of the DAI_IMASK_RE or DAI_IMASK_FE registers allo...

Page 452: ...ources can be any one or more of the interrupt controller s 32 configurable channels DAI_INT31 0 For more information see Inter rupt Controller Registers on page A 149 The DAI triggers two interrupts...

Page 453: ...nterrupt sources requires service Reading the DPI s interrupt latches DPI_IMASK clears the inter rupts Read to Clear bit type Therefore the ISR must service all the interrupt sources it discovers That...

Page 454: ...cribe features that can be used to help in debug ging the DAI DAI Shadow Registers The DAI_IMASK_L_SH and DAI_IMASK_H_SH shadow registers are provided for the DAI_IMASK_L and DAI_IMASK_H registers res...

Page 455: ...al Routing for Loopback SRU SRU2 External Routing for Loopback DAI IDP N A N A N A SPORT Yes SPORTx_xx_O SPORTx_xx_I SPORTx_xx_O DAI_PBxx_I DAI_PBxx_O SPORTx_xx_I S PDIF Tx Rx No DIT_O DIR_I DIT_O DAI...

Page 456: ...unit is controlled by writing values that correspond to signal sources into bit fields that fur ther correspond to signal inputs The SRU is arranged into functional groups such that the registers that...

Page 457: ...mple code is available on the Analog Devices Web site There is a macro that has been created to connect peripherals used in a DAI configuration This code can be used in both assembly and C code See th...

Page 458: ...is phase locked channel to channel I2 S DATA INTO SHARC CORE AC3 Dolby Digital decompression algorithm is executed in software 5 1 channel surround sound sampled at 48 KHz SPORT0 I2 S DATA 3 STEREO PA...

Page 459: ...frame synchronization options the SPORTs allow a variety of serial communi cation protocols and provide a glueless hardware interface to many industry standard data converters and codecs The interfac...

Page 460: ...ial port configurable as either transmitters or receivers Each serial port can also be con figured as two receivers or two transmitters permitting two Transmission Full Duplex No Access Type Data Buff...

Page 461: ...Chaining on page 2 32 DMA Chain insertion mode allows the SPORTs to change DMA priority during chaining see Enter DMA Chain Insertion Mode on page 10 56 Data words between 3 and 32 bits in length eith...

Page 462: ...I O I O Transmit Receive Serial Clock This signal can be either internally or externally generated SPORT7 0_FS_I O I O Transmit Receive Frame Sync The frame sync pulse initiates shifting of serial dat...

Page 463: ...d sources but cannot route their own clocks to other SPORTs or other peripher als internally through the SRU If SPORTs 6 and 7 are needed externally they have to be routed through the DAI pins Table 1...

Page 464: ...SPORTx_CLK and frame sync SPORTx_FS signals when the SPORT is configured as a master receiver By correctly programming the signal routing unit SRU clock and frame sync registers the reflection sensit...

Page 465: ...Control Registers SPCTLx The SPCTLx registers control serial port modes and are part of the SPCTLx transmit and receive control registers Other bits in these registers set up DMA and I O processor rel...

Page 466: ...set the multi channel frame delay Master Clock Divider Registers DIVx The DIVx registers contain divi sor values that determine frequencies for internally generated clocks and frame syncs If your sys...

Page 467: ...to zero Use the following equation to determine the value of CLKDIV given the PCLK frequency and desired serial clock frequency CLKDIV PCLK 4 SCLK 1 If the serial clock of SPORT SCLK is required as g...

Page 468: ...on SPORTs to drive ADCs DACs in high fidelity audio systems Use the precision clock generator PCG instead Slave Mode Exercise caution when operating with externally generated transmit clocks near the...

Page 469: ...of channel A and channel B on a particular SPORT must be the same Serial communications are synchronized to a clock signal Every data bit must be accompanied by a clock pulse Each serial port can gene...

Page 470: ...us data receive and transmit signals Data Types and Companding Linear transfers occur in the primary channel if the channel is active and companding is not selected for that channel Companded transfer...

Page 471: ...ORTx_CLK SPORTx_FS SPORTx_DB SPTRAN CNTL SPORTx_CLK SPORTx_FS SPORTx_DA_OUT SPORTx_DA_IN PM DM DATA BUS TXSPxA TRANSMIT DATA BUFFER HARDWARE COMPANDING COMPRESSION SPORTS 0 2 4 6 ONLY TRANSMIT SHIFT R...

Page 472: ...led the data in the RXSPxA buffers is the right justified sign extended expanded value of the eight received LSBs A write to TXSPxA compresses the 32 bit value to eight LSBs zero filled to the width o...

Page 473: ...tput shift register Receive Path If the serial data signal is configured as a serial receiver SPTRAN 0 the receive portion of the SPORT shifts in data from the SPORTx_DA or SPORTx_DB signal synchronou...

Page 474: ...pling receive data and frame syncs setting CKRE to 1 in the SPCTLx register selects the rising edge of SPORTx_CLK When CKRE is cleared 0 the processor selects the falling edge of SPORTx_CLK for sampli...

Page 475: ...The transmitter for example drives clock and frame sync called master while the receiver is slave sampling these data After the slave is sampled the FS the SLEN word counter is reloaded to the maximum...

Page 476: ...control register determines the frame sync source When IFS IMFS is set 1 the corresponding frame sync signal is gener ated internally by the processor and the SPORTx_FS signal is an output The frequen...

Page 477: ...e for the first valid frame after the SPORT is enabled and applicable to both level and edge sensitive frame syncs This feature is enabled by setting the frame sync edge detec tion bit FSED bit 2 in t...

Page 478: ...the next frame sync is generated This mode of operation allows data to be transmitted only at specific times When DIFS 0 and SPTRAN 0 a receive SPORTx_FS signal is generated only when receive data bu...

Page 479: ...onality change based on the SPORT operating mode See the mode specific section for the bit names and their functions Pairings of SPORTs 0 and 1 2 and 3 4 and 5 and 6 and 7 are only used in loopback mo...

Page 480: ...de Multichannel Mode Control 0 SPEN_A Reserved 1 2 DTYPE Reserved DTYPE 3 LSBF Reserved LSBF 4 8 SLEN 9 PACK 10 ICLK MSTR ICLK 11 OPMODE 12 CKRE Reserved CKRE 13 FSR Reserved 14 IFS Reserved IMFS 15 D...

Page 481: ...Lx register enables the B channels 4 In multichannel mode the bit 0 MCEA in the SPMCTLx register enables the A channels and the bit 23 MCEB in the SPMCTLx register enables the B channels 5 The OPMODE...

Page 482: ...but have a different name depending on the operating mode Further some bits are used in some modes but not others For reference see Table 10 6 on page 10 22 Table 10 7 and Serial Port Registers on pag...

Page 483: ...bits in the SPCTLx register enable and configure standard serial mode operation Internal Clock ICLK Internal Frame Sync IFS Frame Sync Required FSR Sampling Edges Frame Sync data CKRE Logic Level Fram...

Page 484: ...rial port communications The FSR transmit frame sync required bit determines whether frame sync signals are required Active low or active high frame syncs are selected using the LFS bit This bit is lo...

Page 485: ...nd the first bit of the receive data word is latched in the serial clock cycle after the frame sync is asserted The frame sync is not checked again until the entire word has been transmitted or receiv...

Page 486: ...nter nally generated frame syncs remain asserted for the entire length of the data word in late framing mode Externally generated frame syncs are only checked during the first bit They do not need to...

Page 487: ...signal changes To transmit or receive words continuously in left justified mode load the FSDIV register with SLEN 1 For example for 8 bit data words set FSDIV 7 Timing Control Bits Several bits in th...

Page 488: ...nsmitter sends the MSB of the next word in the same clock cycle as the word select SPORTx_FS signal changes To transmit or receive words continuously in I2S mode load the FSDIV register with SLEN 1 Fo...

Page 489: ...strates timing in I2 S mode In this example case OPMODE 1 LAFS 1 and L_FIRST 0 Multichannel Mode The processor s serial ports offer a multichannel mode of operation which allows the SPORT to communica...

Page 490: ...els of SPORT1 3 5 and 7 are capable of expansion only and the primary A channels of SPORT0 2 4 and 6 are capable of compression only 2 Receive comparison is not supported Clocking Options In multichan...

Page 491: ...between the frame sync pulse and the first data bit in multichannel mode The value of MFD is the number of serial clock cycles of the delay Multichannel frame delay allows the processor to work with...

Page 492: ...2 slots SPORT1A drives data to DAC2 during slot 3 2 which asserts TDV for 2 slots SPORT1B receives data from ADC during slot 3 0 Transmit Data Valid Output In the ADSP 214xx processors each SPORT has...

Page 493: ...ter enable and configure multichannel mode Frame Delay MFD Number of multichannel channels NCH Internal Clock ICLK Internal Frame Sync IMFS Sampling Edges Frame Sync Data CKRE Logic Level Frame Sync L...

Page 494: ...d select registers are 32 bits in length These registers provide channel selection for 128 32 bits x 4 channels 128 channels Setting a bit enables that channel so that the serial port selects its word...

Page 495: ...st active channel channel 2 does not occur However for other channels companding occurs correctly Packed Mode A packed mode is available in the SPORT and used for audio codec com munications using mul...

Page 496: ...he serial clock edge is used for sampling or driving serial data and or frame syncs This selection is performed using the CKRE bit in the SPCTL register Frame Sync Options The frame sync period in pac...

Page 497: ...d to configure timing options in packed mode Frame Delay MFD Number of multichannel channels NCH Data Transfers Serial port data can be transferred for use by the processor in two different methods Co...

Page 498: ...s TXSP7 0A TXSP7 0B are the 32 bit transmit data buffers for SPORT7 0 respectively These buffers must be loaded with the data to be transmitted if the SPORT is configured to transmit on the A and B ch...

Page 499: ...e to a full transmit buffer the access is delayed until the buffer is accessed by the external I O device This delay is called a core processor hang If you do not know if the core processor can access...

Page 500: ...serial port is disabled Disable the serial port when writing to the receive buffer or reading from the transmit buffer Data Buffer Packing Received data words of 16 bits or less may be packed into 32...

Page 501: ...orms the data transfer from internal memory to from the appropriate buffer depending on the SPTRAN bit setting If the inactive SPORT data buffers are read or written to by core while the port is being...

Page 502: ...verriden The frame sync is driven off chip and the data output are zero with the DERRx bit set Internal Memory DMA Transfers SPORT DMA provides a mechanism for receiving or transmitting an entire bloc...

Page 503: ...are assigned higher priority than all other DMA channels for example the SPI port because of their relatively low service rate and their inability to hold off incoming data Having higher priority caus...

Page 504: ...DMA parameter registers as shown in Table 2 14 on page 2 14 Load the II IM and C registers with a starting address for the buffer an address modifier and a word count respectively The register contai...

Page 505: ...chaining occurs independently for the transmit and receive channels of each serial port Each SPORT DMA channel has a chaining enable bit SCHEN_A or SCHEN_B that when set 1 enables DMA chaining and wh...

Page 506: ...t a new DMA or DMA chain within the current chain without effecting the current DMA transfer Chain insertion mode operates the same as non chained DMA mode When the current DMA transfer ends an interr...

Page 507: ...zero with the DERRx bit set Interrupts This section handles the various scenarios in which an interrupt is trig gered Both the core and DMA are able to generate data interrupts for receive or transmit...

Page 508: ...he corresponding inter rupt latch bit in the IRPTL or LIRPTL registers must be cleared in case the interrupt has occurred in the same time period SPORT interrupts occur on the second peripheral clock...

Page 509: ...ined DMA Error Detection Similar to previous SHARC processors the SPORTs can return the status of data buffer underflow and overflow conditions Additionally the SPORTs can also detect frame syncs that...

Page 510: ...sync error occurs Note that a frame sync error is not detected in following cases When there is no active data transmit receive and the frame sync pulse occurs due to noise in the input signal This i...

Page 511: ...nding channel by itself for DERR_A DERR_B 2 By writing a 1 to the interrupt status bits in the SPERRCTLx register When sticky bits are cleared interrupts are also cleared Only one error interrupt is c...

Page 512: ...igured as a transmitter the other must be configured as a receiver For example SPORT0 can be a transmitter and SPORT1 can be a receiver for internal loopback Or SPORT0 can be a receiver and SPORT1 can...

Page 513: ...on This delay does also apply in slave mode external clock frame sync for synchronization Multichannel and packed operation is activated 3 serial clock cycles SCLK after the MCEA or MCEB bits are set...

Page 514: ...the chain pointer register which starts the chain 4 Write to the SPCTLx register by setting the DMA enable bit to one and the chaining enable bit to one Setting these bits loads the DMA parameter reg...

Page 515: ...ration configure the DMA parameter registers Index Modify and Count For DMA chaining initialize the chain pointer register with the index register for the first chain 4 Configure the transmitter SPORT...

Page 516: ...register or the SPMCTL1 register The following steps should be taken to port the code to the ADSP 214xx products 1 Instead of programming SPMCTLxy only program both SPMCTLx and SPMCTLy 2 In previous p...

Page 517: ...he MFD bit field to one and the NCH bit field according to the channels in the SPMCTLx register The MFD bit field and the L_FIRST bit allow programs to manipulate the timing as follows 1 The MFD bit f...

Page 518: ...ata values into the SPORT buffers To compress data in place without transmitting use the following procedure 1 Set the SPTRAN bit to 1 in the SPCTLx register The SPEN_A and SPEN_B bits should be 0 2 E...

Page 519: ...acing the serial port to a codec requires little additional programming effort If companding is not selected two formats are available for received data words of fewer than 32 bits one that fills unus...

Page 520: ...Programming Model 10 62 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 521: ...sample rate converters ASRC and the S PDIF transceiver to the internal mem ory of SHARC The IDP specifications are shown in Table 11 1 Table 11 1 IDP Port Specifications Feature SIP PDAP Connectivity...

Page 522: ...justified for serial input ports The PDAP supports four data packing modes for parallel data The PDAP supports a maximum of 20 bits Provides two data transfer types through DMA or interrupt driven tr...

Page 523: ...ternal Nodes Type Description PDAP_CLK_I I Parallel Data Acquisition Port Clock Input Positive or negative edge of the PDAP clock input is used for data latching depending on the IDP_PDAP_CLKEDGE bit...

Page 524: ...er there is 32 bit data available for transfer to the IDP FIFO The width of this pulse is equal to 2 x PCLK cycles This signal can be used to synchronize external requests for new PDAP data Note that...

Page 525: ...s brief descriptions of the major registers For com plete information see Input Data Port Registers on page A 174 Table 11 5 IDP DAI SRU Signal Connections Internal Node DAI Group SRU Register Inputs...

Page 526: ...inputs The eight channels are automatically multiplexed into a single 32 bit by eight deep FIFO Data is always for matted as a 64 bit frame and divided into two 32 bit words The serial protocol is des...

Page 527: ...nel is independent and contains a separate clock and frame sync input The IDP provides an easy way to pump serial data into on chip memory since it is less complex than the traditional SPORT mod ule l...

Page 528: ...P PDAP DMA mode SIP PDAP DMA ping pong mode SIP PDAP Table 11 7 IDP Operation Modes IDP_CTL0 Global Control IDP_CTL1 Channel Control IDP_PP_CTL IDP Operation Modes IDP_EN IDP_ DMA_EN IDP_ENx IDP_ DMA_...

Page 529: ...ata flow for IDP channel 0 where either the PDAP or serial input can be selected Data Hold When the PDAP_HOLD signal is high all latching clock edges are ignored and no new data is read from the input...

Page 530: ...tiple latched parallel sub word samples may be packed into 32 bit words for efficiency The frame sync input is used to hold off latching of the next sample that is ignore the clock edges The data then...

Page 531: ...can be up to 16 bits wide On clock edge 1 bits 19 4 are moved to bits 15 0 16 bits On clock edge 2 bits 19 4 are moved to bits 31 16 16 bits This mode sends one packed 32 bit word to FIFO for every tw...

Page 532: ...clock edges On clock edge 1 bits 19 10 are moved to bits 9 0 10 bits On clock edge 2 bits 19 9 are moved to bits 20 10 11 bits On clock edge 3 bits 19 9 are moved to bits 31 21 11 bits This mode send...

Page 533: ...moved to bits 15 8 On clock edge 3 bits 19 12 are moved to bits 23 16 On clock edge 4 bits 19 12 are moved to bits 31 24 This mode sends one packed 32 bit word to FIFO for every four input clock cycle...

Page 534: ...ed DMA channels can sort and transfer data This method of moving data from the IDP FIFO is described in DMA Transfers on page 11 19 Data Buffer The IDP_FIFO register provides information about the out...

Page 535: ...rrupt when more than a speci fied number of words are in the FIFO This interrupt signals the core to read the IDP_FIFO register The number of data samples in the FIFO at any time is reflected in the I...

Page 536: ...atting data com pliant with the IEC 90958 S PDIF and AES3 standards An additional bit identifies the left right one half of the frame If the data is not in IEC standard format the serial data can be a...

Page 537: ...ght channels The eight groups of three bits indicate the mode of the serial input for each of the eight IDP channels Figure 11 8 and Figure 11 7 shows the IDP data buffer input format for the SIP depe...

Page 538: ...ate the first left channel of each frame In either mode the left channel has bit 3 set 1 and the right channel has bit 3 cleared 0 PDAP Data Buffer Format If the PDAP module is enabled the IDP data bu...

Page 539: ...eared 0 when transferring data to internal memory through the DMA However bit 3 still contains the left right status infor mation In the case of PDAP data or 32 bit I2 S and left justified modes these...

Page 540: ...rs have these functions Internal index registers IDP_DMA_Ix Index registers provide an internal memory address acting as a pointer to the next internal memory location where data is to be written Inte...

Page 541: ...tten Internal modify registers IDP_DMA_Mx Modify registers provide the signed increment by which the DMA controller post modifies the corresponding internal memory Index register after each DMA write...

Page 542: ...is ignored by the DMA machine This feature is provided to avoid stalling the DMA of other channels which are still in an active DMA state To avoid data loss in the finished channel programs can clear...

Page 543: ...ear the interrupt latch appropriately Note that many interrupts are combined in the DAI interrupt Refer to Inter rupts on page 9 32 Threshold Interrupts When using the interrupt scheme the IDP_NSET bi...

Page 544: ...t to the DAI interrupt An interrupt is generated at the end of a DMA which is cleared by read ing the DAI_IMASK_x registers FIFO Overflow Interrupts If the data out of the FIFO either through DMA or c...

Page 545: ...e control When there is no data in the FIFO reading the IDP_FIFO register causes the core to hang This condition continues until the FIFO contains valid data Set ting the IDP_BHD bit 1 prevents the co...

Page 546: ...fect latency is a combination of the write effect latency core access plus the peripheral effect latency peripheral specific Write Effect Latency For details on write effect latency see the SHARC Proc...

Page 547: ...om the DAI pins or the DATA pins if the PDAP is used IDP_PDAP_CLKEDGE bit bit 29 in the IDP_PP_CTL register to specify if data is latched on the rising or falling clock edge if the PDAP is used Starti...

Page 548: ...e IDP_EN bit bit 7 in the IDP_CTL0 register and the IDP_ENx bits in the IDP_CTL1 register In older SHARC processors the IDP starts shifting data before the IDP is enabled However the shifted data is l...

Page 549: ...n the IDP_CTL1 register 2 While the global IDP_DMA_EN and the IDP_EN bits are cleared 0 set the values for the DMA parameter registers that correspond to channels 7 0 3 Keep the clock and the frame sy...

Page 550: ...ond to channels 7 0 3 Keep the clock and the frame sync input of the serial inputs and or the PDAP connected to LOW by setting proper values in the SRU registers 4 Refer to Setting Miscellaneous Bits...

Page 551: ...at the same time as the IDP DMA b As each DMA channel completes a corresponding bit in either the DAI_IMASK_L or DAI_IMASK_H register for each DMA channel is set IDP_DMAx_INT 3 The program clears 0 t...

Page 552: ...again DMAs in process run to completion If step 5 is not performed and a DMA channel expires during step 4 then when IDP DMA is re enabled step 6 the completed DMA is not reprogrammed and its buffer...

Page 553: ...more the SRC is used to clean up audio data from jittery clock sources such as the S PDIF receiver The SRC specifications are listed in Table 12 1 Table 12 1 SRC Specifications Feature Availability C...

Page 554: ...lock jitter Supports left justified I2S right justified 16 18 20 24 bits and TDM serial port daisy chain modes Accepts 16 18 20 24 bit data Up to 192 kHz sample rate input output sample ratios from 7...

Page 555: ...pherals For normal operation the data clock and frame sync signals need to be routed as shown in Table 12 3 Table 12 2 SRC Pin Descriptions ADSP 214xx Internal Node I O Description SRC3 0_CLK_IP_I Inp...

Page 556: ...They also specify the input and output data format Mute Register SRCMUTE The SRCMUTE register controls the connec tion of the mute in and mute out signal Ratio Registers SRCRATx The SRCRATx registers...

Page 557: ...e write address to the FIFO block and the ramp input to the digital servo loop The ROM stores the coefficients for the FIR filter convolution and per forms a high order interpolation between the store...

Page 558: ...FS_OP SRCx_FS_IP when SRCx_FS_OP SRCx_FS_IP The FIFO also scales the input data to mute and stop muting the SRC The RAM in the FIFO is 512 words deep for both left and right channels An offset of 64 t...

Page 559: ...be able to provide excellent rejection of jitter on the SRCx_FS_IP and SRCx_FS_OP clocks as well as measure the arrival of the SRCx_FS_OP clock within 4 97 ps The digital servo loop also divides the f...

Page 560: ...s by the SRCx_FS_OP SRCx_FS_IP 220 ratio for SRCx_FS_IP SRCx_FS_OP or 220 for SRCx_FS_OP SRCx_FS_IP Once the ROM address rolls over the convolution is complete The convolution is performed for both th...

Page 561: ...d I2 S and right justified 16 18 20 24 bit modes Additionally the serial interfaces support TDM mode for daisy chaining multiple SRCs to a processor The serial output data is dithered down to 20 18 or...

Page 562: ...JUSTIFIED MODE SELECT NUMBER OF BITS PER CHANNEL LEFT JUSTIFIED MODE 16 BITSTO 24 BITS PER CHANNEL NOTES 1 LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY fS 2 3 PLEASE NOTETH...

Page 563: ...f SRCs that can be daisy chained together is limited by the maximum frequency of SRCx_CLK_xx_I refer datasheet for exact value For example if the maximum frequency of SRCx_CLK_xx_I is X MHz and the ou...

Page 564: ...ct to each other This mode can also be used for passing through non audio data since no processing is performed on the input data in this mode Matched Phase Mode ADSP 21488 The matched phase mode of t...

Page 565: ...ata 32 bit subframe con tains 24 bit data and 8 bits matched phase The slave SRCs receive the 8 bit matched phase bits instead of their own internally derived ratio if their SRCx_MPHASE bits set to 1...

Page 566: ...ata This is shown in Figure 12 6 Group Delay When multiple SRCs are used with the same serial input port clock and the same serial output port clock the hysteresis causes different group delays phase...

Page 567: ...ate can be calculated from the RAM word depth and GRPDLYS as 512 16 64 taps 7 75 1 Muting Modes The mute feature of the SRC can be controlled automatically in hardware using the MUTE_IN signal by conn...

Page 568: ...h the S PDIF receiver peripheral to determine when the input should mute Each SRC is connected to the S PDIF receiver to read the DIR_NOAUDIO bits When the DIR_NOAUDIO bit is set 1 the SRC immediately...

Page 569: ...and output sample rates are at the same frequency therefore both in and output ports can be routed to the same serial clock and frame sync Effect Latency The total effect latency is a combination of t...

Page 570: ...atency 12 18 ADSP 214xx SHARC Processor Hardware Reference SRC Effect Latency After the ASRC registers are configured the effect latency is 1 5 PCLK cycles minimum and 3 PCLK cycles maximum www BDTIC...

Page 571: ...hree types of information audio data non audio data compressed data and timing information Its specifications are listed in Table 13 1 Table 13 1 S PDIF Specifications Feature Transmitter Receiver Con...

Page 572: ...r optional using external PLL circuit S PDIF receiver direct supports DTS frames of 256 512 1024 2048 and 4096 4096 frames are not supported for the ADSP 2146x processors Managing user status informat...

Page 573: ...es descriptions of the pins used for the S PDIF transmitter Table 13 2 S PDIF Transmitter Pin Descriptions Internal Node I O Description DIT_CLK_I Input Serial clock Controls the rate at which serial...

Page 574: ...s and frames For a complete explanation of S PDIF timing see one of the digital audio interface standards listed in the Features section of this chapter Table 13 3 S PDIF Receiver Pin Descriptions Int...

Page 575: ...s to the required destinations Table 13 5 The biphase encoded data and the external PLL clock inputs to the receiver are routed through the signal routing unit SRU The extracted clock frame sync and d...

Page 576: ...elects Transmit Channel Status Registers DITCHANAx Bx These registers provide status bit information for transmitter subframe A and B in stand alone mode Transmit User Bit Registers DITUSRBITAx Bx The...

Page 577: ...tter Functional Description The S PDIF transmitter shown in Figure 13 1 resides within the DAI and it s inputs and outputs can be routed via the SRU It receives audio data in serial format encloses th...

Page 578: ...lidity bits for both channels may also be controlled by the transmitter control register Optionally the user bit validity bit and channel status bit are sent to the transmitter with each left right sa...

Page 579: ...iety of interfaces Figure 13 2 AES3 Output Block Figure 13 3 Data Packing for I2S and Left Justified Format 7 LRCLK 24 3 24 3 BLK_START M_COUNT BIPHASE_TX_CLK FREQMULT 2 SAMPLE LR BIPHASE ENCODER TX_C...

Page 580: ...king for Right Justified Format 18 Bits Figure 13 7 Data Packing for Right Justified Format 16 Bits Bits 27 4 24 Bit Audio Data 3 2 1 0 Channel Status User Data Validity Bit Block Start Bits 27 8 20 B...

Page 581: ...frame is generated internally The channel status bits come from the channel status buffer registers DITCHANAx and DITCHANBx The user status bits come from the user bits buffers DITUSRBITAx and DITUSR...

Page 582: ...update user bits buffers at any time during the transfer of the current block 1 block 192 frames There are internal buffers to store the user status bits of the current block of transfer In other wor...

Page 583: ...ned by the Audio Engineering Society The AES3 standard effectively defines the data and status bit structure of an S PDIF stream AES3 compliant data is sometimes referred to as AES EBU compliant This...

Page 584: ...of managing the incoming status bit information The S PDIF receiver receives any S PDIF stream with a sampling fre quency range of 32 kHz 15 to 192 kHz 15 range The channel status bits are collected i...

Page 585: ...d clock must be less than 200 ps and if possible less than 100 ps across all the sampling frequencies ranging from 27 2 kHz to 220 8 kHz 32 kHz 15 and 192 kHz 15 Further more once the PLL achieves loc...

Page 586: ...SPDIF receiver is required to detect compressed or non linear audio data according to the AES3 IEC60958 and IEC61937 standards Bit 1 of byte 0 in the DIRSTAT register indicates whether the audio data...

Page 587: ...all DTS frame sizes of 256 512 1024 2048 and 4096 To enable support for 2048 and 4096 DTS frame sizes DTS_CD_4K_EN bit in DIRCTL need to be set In 2146x on chip S PDIF receiver sup ports 256 512 and...

Page 588: ...ecovery Modes The S PDIF receiver extracts audio data channel status and user bits from the biphase encoded AES3 and S PDIF stream In addition a 50 duty cycle reference clock running at the sampling r...

Page 589: ...erated by the transmitter and receiver and processed through the DAI interrupt controller which can generate an interrupt signal using the DAI_IMASK_x registers Table 13 6 provides an overview of S PD...

Page 590: ...five receiver error status bits DAI_IRPTL_x generate an interrupt Receiver Locked DIR_LOCK_INT Validity DIR_VALID_INT No Audio Stream DIR_NOSTREAM_INT CRC Error DIR_CRCERROR_INT Parity or biphase Erro...

Page 591: ...e peripheral effect latency peripheral specific Write Effect Latency For details on write effect latency see the SHARC Processor Programming Reference Programming Model The following sections provide...

Page 592: ...k 192 allowing changes of user bits for the next block 3 Initialize the DITCTL register to enable the data encoding 4 Manually set the block start bit in the data stream once per block 384 words This...

Page 593: ...s to accomplish this are described below 1 Set up interrupts within the DAI so that the S PDIF receiver can generate an interrupt when the stream is reconnected 2 Within the interrupt service routine...

Page 594: ...more than 1 DAI interrupt is being used it is neces sary to determine which interrupt occurred here Interrupt Service Routine for the DAI Hi Priority Inter rupt This ISR triggered when the DIR sets no...

Page 595: ...The two signals generated by each unit are normally used as a serial bit clock frame sync pair Table 14 1 lists the PCG specifications Table 14 1 PCG Specifications Feature PCGA B PCGC D Connectivity...

Page 596: ...c phase 20 bit and pulse width 16 bit Phase shift allows adjustment of the frame sync relative to the serial clock and can be shifted the full period and wrap around Provides pulse width control for a...

Page 597: ...ons Internal Nodes I O Description Inputs CLKIN I External clock input for PCG x PCLK I Internal peripheral clock input for PCG x PCG_SYNC_CLKx_I I External trigger used to enable the frame sync outpu...

Page 598: ...RU_CLK4 9 5 29 connects PCG_EXTB_I to logic low not to PCG_CLKB_0 The clock and frame sync signals of Table 14 3 PCG DAI SRU Connections Internal Nodes DAI Group DPI Group SRU Register Inputs PCG_SYNC...

Page 599: ...he frame sync divider and the upper half of the 20 bit phase value Control Register 1 PCG_CTLx1 Enables the clock and frame sources it includes the clock divider and the lower half of the 20 bit phase...

Page 600: ...r a DAI pin source The clock output is derived from the input to the PCG with a 20 bit divisor Note that the divider is working in normal mode for CLKDIV 1 For CLKDIV 0 1 the divider operates in bypas...

Page 601: ...Sync The following sections describe the use of frame syncs in the PCGs Frame Sync Output Each of the four units A through D also produces a synchronization sig nal for framing serial data The frame...

Page 602: ...he clock input signal Frame sync phase shifting is often required by peripherals that need a frame sync signal to lead or lag a clock signal For example the I2 S protocol specifies that the frame sync...

Page 603: ...e modified Both units must also be disabled in a single atomic instruction as shown below r0 CLKDIV_A PHASE_LO_A dm PCG_CTLA1 r0 r0 FSDIV_A PHASE_HI_A ENCLKA ENFSA program dividers and enable CLK and...

Page 604: ...ulse width of the frame sync output is equal to For even divisors frame sync divisor 2 If the pulse width count is equal to 0 and if FSDIV bit field is odd then the actual pulse width of the frame syn...

Page 605: ...the same time Also assume that the clock divisor value needed to generate the required SCLK is CLKDIV 4 Then for a 32 bit word length the frame sync divisor value should be FSDIV 64 CLKDIV 256 By defa...

Page 606: ...en the positive edges of the clock and frame sync coincide when the clock and frame sync dividers are enabled at the same time using an atomic instruction the divisors of the clock and frame sync are...

Page 607: ...detail below If the STROBEx bit of PCG_PWx register is cleared then the input is directly passed see Figure 14 3 to the frame sync output either inverted or not inverted depending on the INVFSx bit o...

Page 608: ...s at the second rising edge of MISCAx_I following a rising edge of the clock input When the INVFSx bit is set the pulse begins at the second rising edge of MISCAx_I coinciding with or following a fall...

Page 609: ...g cases need to be considered PCLK is the input source In this case if the given trigger event is synchronous to PCLK the delay is 3 PCLK periods If the trigger sig nal is asynchronous with PCLK the d...

Page 610: ...te converter ASRC to interface to an external audio DAC The PCG is configured to provide a fixed ASRC DAC output sample rate of 65 098 kHz The input to the S PDIF receiver is typically 44 1 kHz if sup...

Page 611: ...alling edge of SCLK must always be synchronous with both edges of FS This requires that the phase of the SCLK and FS signals for a com mon PCG PCG A be adjustable While the frequency of the master DAC...

Page 612: ...onfiguration Examples For a CLKIN 33 330 MHz the two PCGs provide the three synchronous clocks PCGx_CLK SCLK and FS for the SRCs and external DAC These divi sors are stored in 20 bit fields in the PCG...

Page 613: ...Effect Latency After the PCG registers are configured the effect latency is shown below The latency to start the CLKOUT depends on the divisor value and input source as described below Input clock th...

Page 614: ...which sequences of software steps required for suc cessful PCG operation Frame Sync Phase Setting The phase unit requires that the clock and FS is enabled simultaneously in an atomic instruction 1 Wri...

Page 615: ...external clock is used to synchronize with the frame sync the frame sync output is not generated until a rising edge of the external clock is sensed Debug Features Care should be taken in cases where...

Page 616: ...Debug Features 14 22 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 617: ...riety of peripheral devices including codecs data converters sample rate converters S PDIF or AES EBU digi tal audio transmitters and receivers LCDs shift registers microcontrollers and FPGA devices w...

Page 618: ...ulti devices in which the ADSP 214xx master processor can be connected to up to four other SPI devices Parallel core and DMA access allow full duplex operation Open drain outputs to avoid data content...

Page 619: ...nections between two devices Table 15 2 SPI Pin Descriptions Internal Node Type Description SPI_CLK_I O SPIB_CLK_I O I O SPI Clock Signal This control line is clock driven by the master and regulates...

Page 620: ...s of the slave s SPI_MISO_I O SPIB_MISO_I O I O SPI Master In Slave Out This data line transmits the output data from the slave device and receives the input data to the master device This data is sh...

Page 621: ...3 SPI DPI SRU2 Signal Connections Internal Node DPI Group SRU2 Register Inputs SPI_CLK_I SPIB_CLK_I SPI_DS_I SPIB_DS_I SPI_MOSI_I SPIB_MOSI_I SPI_MISO_I SPIB_MISO_I Group A SRU2_INPUT1 0 Outputs SPI_...

Page 622: ...systems SPI Status SPISTATx This status register provide information on trans mission errors for the core SPI Baud rate SPIBAUDx For master devices the clock rate is deter mined by the 15 bit value of...

Page 623: ...t edge on SPIx_CLK DPI pin output is not incorrectly chosen as a sampling edge by the slave SPI Table 15 5 shows the correct pin enable to use for a chosen SPI mode All other SPI signals SPIx_MOSI SPI...

Page 624: ...SO pin and transmits using the MOSI pin The other SPI device acts as the SPI slave by receiving new data from the master into its receive shift register using the MOSI pin It transmits requested data...

Page 625: ...er initiation mode is TIMOD selected For a master SPI with CPHASE 0 a transfer starts when either the TXSPI register is written or the RXSPI register is read depending on the TIMOD selection At the st...

Page 626: ...ling edge of SPICLK Single Master Systems Figure 15 2 illustrates how the SHARC processor can be used as the slave SPI device The 16 bit host A Blackfin ADSP BF53x processor is the SPI master The proc...

Page 627: ...nse Multi master mode allows an SPI system to transfer mastership from one SPI device to another In a multi device SPI configuration several SPI ports are connected and any one but only one of them ca...

Page 628: ...n invalidly asserted SPIDS signal it triggers an error handling scenario using the MME bit SPIMME bit for DMA and ISSEN bit to reconfigure the SPI to slave mode and jump into an ISR This ensures that...

Page 629: ...buffer has a word in it Emptying the RXSPI buffer or disabling the SPI port at the same time SPIEN 0 stops the interrupt latch 01 Core Transmit and Receive Initiate new single word transfer upon write...

Page 630: ...S signal repre sents the slave device select input to the processor from the SPI master The diagrams represent 8 bit transfers WL 0 with MSB first MSBF 1 Any combination of the WL and MSBF bits of the...

Page 631: ...ed as a slave select output For example if DS1EN 1 is set SPI_FLG1_O is driven as a slave select At the chip level SPI_FLG1_O can be connected to any of the DPI pins through SRU programming For those...

Page 632: ...between transfers If CPHASE 0 or CHPASE 1 and AUTOSDS 1 all selected outputs are asserted only for the duration of the transfer This is controlled by the internal SPI hardware In this case the SPIFLGx...

Page 633: ...ers T4 is two SPICLK periods This time period is measured from the last active edge of SPICLK of one word to the first active edge of SPICLK of the next word This calculation is independent from the c...

Page 634: ...cases T3 STDC SPI clock period for STDC 0 Data Transfers The SPI is capable of transferring data via the core and DMA The follow ing sections describe these transfer types Buffers The SPI allows 3 di...

Page 635: ...is necessary as the entire 32 bit register is used for the data word Core Buffer Status For core access to SPI master and slave mode operates different 1 If core access to a SPI slave is unable to kee...

Page 636: ...used by using multiple DMA channels the SPI operates according to the states of the SENDZ and GM bits in the SPICTLx register If SENDZ 1 and the transmit buffer is empty the device repeatedly transmit...

Page 637: ...is set at the same time as RXS For a master device SPIF is set one half 0 5 of the SPICLK period after the last SPICLK edge regardless of CPHASE or CLKPL The baud rate determines when the SPIF bit is...

Page 638: ...words until the SPI DMA word count register transitions from 1 to 0 Do not write to the TXSPIx buffer during an active SPI transmit DMA operation because DMA data will be overwritten Similarly do not...

Page 639: ...sequence Writing an address to the CPSPIx registers does not begin a chained DMA sequence unless the IISPI IMSPI CSPI IISPIB IMSPIB and CSPIB registers are initialized SPI DMA is enabled the SPI port...

Page 640: ...bits can be polled Writes to the TXSPIx buffer during an active SPI receive DMA operation are permitted Note the RXS bit is cleared when the RXSPIx buffer is read but the DMA FIFO is not available in...

Page 641: ...C register must be initialized properly to enable DMA interrupts Each of these five interrupts are serviced using the interrupt associated with the module being used The primary SPI uses the SPIHI int...

Page 642: ...nly if SPIRCV 0 or receive buffer overflow ROVF only if SPIRCV 1 During core driven transfers the TUNF and ROVF error conditions do not generate interrupts When DMA is disabled the processor core may...

Page 643: ...wise once SPIEN and SPIMS are set another mode fault error condition will immediately occur The state of the input pin is reflected in the input slave select status bit bit 7 in the SPIFLG register As...

Page 644: ...ble Core receive and transmit transfers Transmit DMA and core receive transfers Core Transmit and DMA receive transfers To loop data back from MOSI to MISO the MISO pin is internally discon nected The...

Page 645: ...Configuration Programs should take the following precautions when changing SPI configurations The SPI configuration must not be changed during a data transfer Change the clock polarity only when no s...

Page 646: ...outputs 2 Before enabling the SPI port programs should specify which of the slave select signals DPI pins to use setting one or more of the required SPI flag select bits DSxEN in the SPIFLGx register...

Page 647: ...oaded with the contents of the TXSPIx registers At the end of the transfer the con tents of the receive shift register are loaded into the RXSPI buffer 3 With each new buffer access the SPI continues...

Page 648: ...t TIMOD 10 The next steps are dependant on whether the access is a core or a DMA access Core Slave Transfers The following steps illustrate SPI operation in slave mode 1 Write the data to be transmitt...

Page 649: ...eps 1 Clear the chain pointer register 2 Configure the TCB associated with each DMA in the chain except for the first DMA in the chain 3 Write the first three parameters for the initial DMA to the IIS...

Page 650: ...ps for switching from transmit to transmit receive DMA With SPI disabled 1 Poll the SPIFE bit in the SPISTAT register If this bit is high the SPI can be disabled 2 Clear the SPICTLx register to disabl...

Page 651: ...T reg ister This ensures that no interrupts occur due to errors from a previous DMA operation 5 Reconfigure the SPICTL register to remove the clear condition on the TXSPI RXSPI registers 6 Configure D...

Page 652: ...If this bit 1 the SPI can be disabled 2 Clear the RXSPIx TXSPIx registers and the buffer status without dis abling the SPI by ORing 0xC0000 with the present value in the SPICTLx registers Use the RXF...

Page 653: ...ng sequence details the steps to respond to this interrupt With SPI disabled 1 Disable the SPI port by writing 0x00 to the SPICTLx registers 2 Disable DMA and clear the DMA FIFO by FIFOFLSH bit in the...

Page 654: ...ts SPIOVF and SPIUNF in the SPIDMACx registers are cleared when a new DMA is configured 4 Reconfigure the SPICTL register to remove the clear condition on the RXSPI TXSPI register bits 5 Configure DMA...

Page 655: ...ware Reference 15 39 Serial Peripheral Interface Ports 5 If bus requester detects the SPI_DS_I pin high it sets the SPIMS bit to get bus mastership 6 The master selects a slave by driving its slave se...

Page 656: ...Programming Model 15 40 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 657: ...igured in three operation modes The timers specifications are shown in Table 16 1 Table 16 1 Timer Specifications Feature Timer1 0 Connectivity Multiplexed Pinout No SRU DPI Required Yes SRU DPI Defau...

Page 658: ...ntrol status registers for synchronous operation of multi ple timers Buffered timer registers Period and Width to allow changes on the fly The core timer is controlled by system registers while the pe...

Page 659: ...age 9 25 Table 16 2 Peripheral Timer Pin Descriptions Internal Node Type Description TIMER1 0_I I Timer Signal This input is active sampled during pulse width and period capture width capture mode or...

Page 660: ...be set indirectly by initializing the period or width values in the appropriate mode The counter should only be read when the respective timer is disabled This prevents erroneous data from being retu...

Page 661: ...are used During the pulse width and period capture WDTH_CAP mode both the period and width values are captured at the appropriate time Since both the width and period registers are read only in this m...

Page 662: ...egisters for each timer are Timer x control TMxCTL register Timer x word count TMxCNT register Timer x word period TMxPRD register Timer x word pulse width TMxW register The timers also share a common...

Page 663: ...Mode MODE 01 Output PWM Wave form 10 Input Waveform 11 Input Event TIMEN 1 Enable Start Timer 0 Disable Timer 1 Enable Start Timer 0 Disable Timer 1 Enable Start Timer 0 Disable Timer PULSE 1 Generat...

Page 664: ...low width pulse waveform is gen erated at the TIMERx signal The timer is actively driven as long as the TIMODE field remains 01 Figure 16 2 shows a flow diagram for PWM_OUT mode When the timer become...

Page 665: ...the PWM waveform and 2 x TMxW is the width If the period and width values are valid after the timer is enabled the count register is loaded with the value resulting from 0xFFFF FFFF width The timer c...

Page 666: ...D and width TMxW registers are programmed with the values of the timer count period and pulse width modulated out put pulse width When the timer is enabled in this mode the TIMERx signal is pulled to...

Page 667: ...it again On the next counter reload all of the timer control registers are read by the timer To generate the maximum frequency on the TIMERx_O output signal set the period value to two and the pulse w...

Page 668: ...PULSE bit in each period Pulse Width Count and Capture Mode WDTH_CAP To enable WDTH_CAP mode set the TIMODE1 0 bits in the TMxCTL regis ter to 10 This configures the TIMERx signal as an input signal w...

Page 669: ..._I signal When the timer detects a first leading edge it starts incrementing When it detects the trailing edge of a waveform the timer captures the current value of the count register TMxCNT 2 and tra...

Page 670: ...it TIMxIRQ gets set when the pulse period value is captured If the PRDCNT bit is cleared the TIMxIRQ bit gets set when the pulse width value is captured If the PRDCNT bit is cleared the first period v...

Page 671: ...register should not be read when the counter is running The operation of the EXT_CLK mode is as follows 1 Program the TMxPRD period register with the value of the maximum timer external count 2 Set th...

Page 672: ...ter reaching the count value 0xFFFF FFFE the TIMxIRQ bit is set and an interrupt is generated The next rising edge reloads the count register with 0xFFFF FFFF TMxPRD again The EXT_CLK timing is shown...

Page 673: ...al A common register latches these interrupts so that a program can determine the interrupt Figure 16 8 EXT_CLK Timing Table 16 5 Timer Interrupt Overview Interrupt Source Interrupt Condition Interrup...

Page 674: ...tructions RTI Interrupt and overflow bits may be cleared simultaneously with timer enable or disable To enable a timer s interrupt set the IRQEN bit in the timer s configuration TMxCTL register and un...

Page 675: ...ents the timer interrupt from being generated When the timer reaches the period value and generates the interrupt reset the processor within the corresponding watchdog s ISR Debug Features The followi...

Page 676: ...ister is loaded according to the operation mode specified in the TMxCTL register When the timer is dis abled the counter registers retain their state when the timer is re enabled the counter is reinit...

Page 677: ...timer s operating mode the polarity of the TIMERx signal and the timer s interrupt behavior Do not alter the operating mode while the timer is running For more infor mation see Timer Configuration Re...

Page 678: ...en 2 x period expires the counter is loaded with 2 x width value again and the cycle repeats When the width or period expires the IRQ bit if enabled is set depending on the PRDCNT bit When IRQ is sens...

Page 679: ...th Note that the first period value will not have been measured when the first width is measured so it is not valid The timer sets and returns a period value of zero in this case When the period expir...

Page 680: ...rts the count down When the period expires it is reloaded with the period value and the cycle repeats Counter counts with each edge of the input wave form asynchronous to PCLK When the period expires...

Page 681: ...modules on two or more processors The serial in parallel out mode can be used to convert the serial data to paral lel Table 17 1 lists the shift register specifications Table 17 1 Shift Register Speci...

Page 682: ...DO allows cascad ing of multiple SR registers SRU routing unit allows the input selection for clock and data from SPORT7 0 PCGA B DAI Pin buffer 8 1 or external SR pins Pin buffers remain three stated...

Page 683: ...from PCGA B then SPORT0 7 generates the SR_LAT and SR_SDI signals If SR_SCLK and SR_LAT come from PCGA B then SPORT0 7 generates the SR_SDI signal Configure CKRE 1 when using SPORT as a source of SR_S...

Page 684: ...gures the clock source For more information see Clock Routing Register SRU_CLK_SHREG on page A 145 Data Routing Register SRU_DAT_SHREG Configures the data source For more information see Data Routing...

Page 685: ...utput SR_SDO_O for cascading A common active low asynchronous reset SR_CLR_I is provided for 18 bit shift register and for 18 bit latch As shown in the Figure 17 1 the latch has 18 parallel outputs to...

Page 686: ...utput By default if all the SR_SDO_SEL bits are cleared the LSB data is output This mode is for use ful if multiple SR registers need to be cascaded Figure 17 1 SR Block Diagram PCG_CLKA_O 18 STAGE SH...

Page 687: ...e output whenever this bit is set The data in each flip flop is transferred to the respective latch on a posi tive going transition of the SR_LAT_I input If both clocks are connected together the shif...

Page 688: ...ister Effect Latency After the SR register is configured the maximum effect latency is 2 PCLK cycles Programming Model Since the SR_CTL SRU_CLK_SHREG and SRU_DAT_SHREG register signals come from the p...

Page 689: ...mplement either a real time watch or a life counter The RTC specifications are shown in Table 18 1 Table 18 1 RTC Specifications Feature Availability Connectivity Multiplexed Pinout No SRU DAI Require...

Page 690: ...rd two pin interface with external 32 768 KHz crystal 6 pF capacitor on each pin and 100 M resistor between the pins RTC Power switches to that of I O Supply when chip is powered on saving battery lif...

Page 691: ...I pin to EGND tie the RTCVDD pin to EVDD and leave the RTXO pin unconnected Register Overview This section provides basic information on the RTC control and status registers only Complete bit informat...

Page 692: ...ts the other three counters when appropriate The 32768 day counter is incremented each day at midnight 23 hours 59 minutes 59 seconds Interrupts can be issued periodically either every second every mi...

Page 693: ...ers The 32768 day counter is incremented each day at midnight during change from 23 59 59 The counter operates on the RTC supply either Figure 18 1 RTC Block Diagram DAYS COUNTER ALARM EVENT 24 HOURS...

Page 694: ...e correct time by a software write into the RTC_CLOCK register Once set the counters maintain time as long as the RTC supply is valid Partitioning The RTC is partitioned into two blocks The counting a...

Page 695: ...larm hour minute and second When the alarm interrupt is enabled the RTC generates an inter rupt each day at the time specified The second alarm feature allows the application to specify a day as well...

Page 696: ...y day when the clock register changes from a Day Hour Min Sec value of XXX 23 59 59 to YYY 00 00 00 It functions by adding or subtracting an integer number of seconds maximum of 7 from the start of th...

Page 697: ...only be in integer multiples of seconds Zero to seven seconds can be added or subtracted using 4 bits The MSB indicates addition 0 or subtraction 1 The three LSBs indi cate number of seconds 0 7 repr...

Page 698: ...ndix B Peripheral Interrupt Control The RTCI source bit is used to connect the RTC interrupt to the peripheral interrupt inputs of the core Table 18 2 pro vides and overview of RTC interrupts Service...

Page 699: ...be programmed to provide an interrupt at the completion of all pending writes to any of the 1 Hz registers RTC_CLOCK and RTC_INIT Interrupts can be individually enabled or disabled using the RTC inter...

Page 700: ...y see the SHARC Processor Programming Reference Real Time Clock Effect Latency After the RTC registers are configured the effect latency is 2 PCLK cycles Programming Model Writes of the alarm clock st...

Page 701: ...cillator is powered down or when the RTC_READEN bit is set During initialization after a write of the RTC_INIT register make sure that the WR_PEND bit is cleared before attempting writes to other regi...

Page 702: ...r down and needs to know the status of the RTC 5 Whenever the ADSP 2147x processor core wakes up from power down the values of the RTC_CLOCK RTC_ALARM and RTC_SWTCH registers is zero until the first s...

Page 703: ...d after waking from Deep Sleep This is valid as long as the RTC 1 Hz clock is running Use this flag or interrupt to validate the other flags Write Complete Always valid Write Pending Status Always val...

Page 704: ...lt in any spurious interrupts from a previous state 1 Wait for 1 Hz tick 2 Write new values for RTC_CLOCK RTC_ALARM and or RTC_SWCNT 3 Write 1s to clear the RTC_CLOCK flags for Alarm Day Alarm Stop wa...

Page 705: ...n of a system reset if the timer expires before being reloaded by software The WDT specifications are shown in Table 19 1 Table 19 1 Watchdog Timer Specifications Feature Availability Connectivity Mul...

Page 706: ...own clock WDT_CLKIN that is independent from the SHARC CLKIN and any other clock derived from CLKIN An internal oscillator to provide the clock input This internal oscillator provides a 2 MHz typical...

Page 707: ...For more information see Peripheral Timer Registers on page A 269 Control Register WDTCTL The control register is a 32 bit system memory mapped register used to configure the watchdog timer Any writes...

Page 708: ...ation see Clocking on page 19 4 Internal oscillator is only supported on ADSP 2147x processor models Clocking The WDT provides three options for the clock source 1 External clock source can be provide...

Page 709: ...internal peripherals After an external reset the WDT must be disabled by default Software must be able to determine if the watchdog was the source of the hardware reset by interrogating a status bit i...

Page 710: ...d until the next time hardware reset is applied The trip counter is not cleared by the WDT generated reset This gives soft ware the ability to count the number of WDT generated resets using the CURTRI...

Page 711: ...e write effect latency core access plus the peripheral effect latency peripheral specific Write Effect Latency For details on write effect latency see the SHARC Processor Programming Reference Watchdo...

Page 712: ...ent time must be provided for the write to the WDTCURCNT reg ister to occur 2 5 WDTCLK cycles max before enabling WDT 4 Enable the watchdog timer in WDTCTL 5 Lock the WDT configuration registers by wr...

Page 713: ...ignored but the write command cause the WDTCURCNT register to be reloaded from the WDTCNT register If the watchdog is enabled with a zero value loaded to the counter WDT expires immediately and reset...

Page 714: ...Programming Model 19 10 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 715: ...hown in Table 20 1 Table 20 1 UART Specifications Feature Availability Connectivity Multiplexed Pinout No SRU DAI Required No SRU DAI Default Routing N A SRU2 DPI Required Yes SRU2 DPI Default Routing...

Page 716: ...he functional block Compatible with the RS 232 and RS 485 Standards Data packing support for efficient memory usage Full duplex DMA operation Multiprocessor communication using 9 bit addressing Autoba...

Page 717: ...are byte wide registers that are mapped as half words with the most signifi cant byte zero filled Line Control Register UARTxLCR Controls the format of the data character frames It selects word lengt...

Page 718: ...us of core or DMA operation Receive Status Register UARTxRXSTAT Returns status of core or DMA operation Interrupt Identification Status Register UARTxIIR Provides status of all interrupts and combines...

Page 719: ...divide factors required to support most stan dard baud rates Careful selection of PCLK frequencies that is even multiples of desired baud rates can result in lower error percentages Functional Descrip...

Page 720: ...pts or polling The DMA method requires minimal software intervention as the DMA engine itself moves the data For more information see DMA Transfers on page 20 13 Either one of the peripheral timers ca...

Page 721: ...t of received and transmitted character frames is controlled by the line control register UARTLCR Data is always transmitted and received least significant bit LSB first Figure 20 2 shows a typical ph...

Page 722: ...ively from the transmitter Packing is available in both I O and DMA modes A control bit UARTPKSYN can be used to re synchronize the packing For information on using the UART for DMA transfers see DMA...

Page 723: ...ated in software to detect errors The reception may be stopped when the receiver receives another address which is different from its own In 9 bit mode the address detect interrupt can be generated wh...

Page 724: ...ding Registers UARTTHR A write to the UART transmit holding register UARTTHR initiates the transmit operation The data is moved to the internal transmit shift regis ter UARTTSR where it is shifted out...

Page 725: ...the data and any status are updated and the UARTRSR register is transferred to the UART receive buffer register UARTRBR shown in Figure 20 4 After the transfer of the received word to the UARTRBR buff...

Page 726: ...acter at time To prevent any loss of data and misalignments of the serial data stream the UART line status register UARTLSR provides two status flags for hand shaking UARTTHRE and UARTDR The UARTTHRE...

Page 727: ...y The software does not have to move data it just has to set up the appropriate transfers either through normal DMA or DMA chaining Software can write up to two words into the UARTTHR register before...

Page 728: ...nal memory and a new DMA starts The index of the memory location is written in the chain pointer register DMA parameter values reside in consecutive mem ory locations as shown in Table 2 16 on page 2...

Page 729: ...n Interrupt Completion Interrupt Acknowledge Default IVT DPI UART TX RX DMA RX TX done Core RX buffer full Core TX buffer empty Core RX Error overrun parity framing break DMA RX Error overrun parity f...

Page 730: ...programmed to configure them This method shown in Listing 20 2 uses the PICR register with the code value of the UART_RXI or UART_TXI interrupts Listing 20 2 Enabling UART Interrupts bit set mode1 IRP...

Page 731: ...or receive and trans mit in core mode all interrupts are grouped as a single receive interrupt UARTRXI only The UART interrupt enable register UARTIER is used to enable requests for core system handli...

Page 732: ...oftware routine This can be established by globally assigning all UART interrupts to the same inter rupt priority using the programmable interrupt priority control registers Please note the special ro...

Page 733: ...for the following cases When UARTRBR is full On a receive overrun error On a receive parity error On a receive framing error On a break interrupt RXSIN held low When UARTTHR is empty An address detec...

Page 734: ...BRSH return exactly the same contents as the main register but without changing the register s status in any way Shadow Buffer Because of the destructive nature of reading the read buffer UARTxRBR a s...

Page 735: ...ramming procedures for core and DMA data transfers Autobaud Detection When the baud rate of the incoming signal is not known one of the gen eral purpose timers can be used in width capture mode to aut...

Page 736: ...programmed with the calculated baud rate Programming Model for DMA Transfers The following is the general procedure for transferring data using DMA 1 Clear the UARTTXCTL UARTRXCTL register to zero 2 C...

Page 737: ...eros Notes on Using UART DMA The following should be noted when performing DMA through the UART DMA can be interrupted by resetting the UARTDEN bit but none of the other control settings should be cha...

Page 738: ...TIER registers to generate interrupt when the trans mit buffer is empty and or the receive buffer is full 4 Program the PICR registers to map the UART interrupt directly or Configure the DPI_IRPTL reg...

Page 739: ...To preserve processor bandwidth the TWI controller can be set up with transfer initiated interrupts to service FIFO buffer data reads and writes only Protocol related interrupts are optional The TWI s...

Page 740: ...ice FIFO buffer data reads and writes Protocol related interrupts are optional The TWI mas ter controller includes the features described in the list that follows Simultaneous master and slave operati...

Page 741: ...externally interface the TWI controller to the I2 C bus The interface is simple and no other external connections or logic are required Table 21 2 TWI Pins Internal Node Type Description TWI_CLK_I I...

Page 742: ...the generated clock is 1 10 MHz or 100 ns CLKDIV TWI_CLOCK period 10 MHz time reference For example for an TWI_CLOCK of 400 kHz period 1 400 kHz 2500 ns and an internal time reference of 10 MHz perio...

Page 743: ...rol Register TWIMCTL Controls the logic associ ated with master mode operation Bits in this register do not affect slave mode operation and should not be modified to control slave mode functionality M...

Page 744: ...eral interface supports the transfer of 32 bit wide data and is used by the processor in the support of register and FIFO buffer reads and writes The register block contains all control and status bit...

Page 745: ...data sheet see the I2 C bus specification from Philips as well as for TWI_CLOCK clock generation The clock generation module is used to generate an external serial clock TWI_CLOCK when in master mode...

Page 746: ...begins The TWI controller only issues a clock during master mode operation and only at the time a transfer has been initiated If arbitration for the bus is lost the serial clock output immediately th...

Page 747: ...ters initiate a transfer arbitration for the bus begins This is illustrated in Figure 21 5 The TWI controller monitors the serial data bus TWI_DATA while the TWI_CLOCK is high If TWI_DATA is determine...

Page 748: ...and recognizes these transitions Typically start and stop conditions occur at the beginning and at the conclusion of a transmission with the exception of repeated start combined transfers as shown in...

Page 749: ...stop bit is set during an active master transfer the TWI con troller issues a stop condition as soon as possible to avoid any error conditions as if data transfer count had been reached Slave Mode Add...

Page 750: ...ite access to the TXTWI8 register adds only one transmit data byte to the FIFO buffer With each access the transmit status TWITXS field in the TWIFIFOSTAT register is updated If an access is performed...

Page 751: ...e TWI 8 bit FIFO receive register RXTWI8 shown in Figure 21 9 holds an 8 bit data value read from the FIFO buffer Receive data is read from the corresponding receive buffer in a first in first out ord...

Page 752: ...ed and byte 1 is the second byte received With each access the receive status TWIRXS field in the TWIFIFOSTAT register is updated to indi cate it is empty If an access is performed while the FIFO buff...

Page 753: ...d timing that are different When fast mode is enabled using the TWIFAST bit the following timings are modified to meet the electrical requirements Serial data rise times before arbitration evaluation...

Page 754: ...TWI_INT dm DPI_IRPTL_RE ustat1 unmasks TWI interrupt TWI The TWI receive and transmit interrupts can also be programmed through the peripheral interrupt control registers PICRx as separate inter Table...

Page 755: ...t imask P1I unmasks P1I interrupt ustat1 dm PICR0 route TWII 0x17 to P1I bit set ustat1 P1I4 P1I2 P1I1 P1I0 bit clr ustat1 P1I3 dm PICR0 ustat1 Interrupt Sources The six different types of interrupts...

Page 756: ...nstruction rti Debug Features The following section provides information on debugging features avail able with the TWI Buffer Hang Disable To support debugging buffer transfers the processors have a b...

Page 757: ...ing sections include information for general setup slave mode and master mode as well as guidance for repeated start conditions General Setup General setup refers to register writes that are required...

Page 758: ...register Indicate if transmit or receive FIFO buffer interrupts should occur with each byte transmitted received or with each 2 bytes transmitted received 4 Program the TWIIMASK register Enable bits...

Page 759: ...ansmit ted during the address phase of the transfer 2 Program the TXTWI8 or TXTWI16 registers This is the initial data transmitted It is considered an error to complete the address phase of the transf...

Page 760: ...t address sets the direction to master transmit uses standard mode timing and transmits 8 data bytes before generating a stop condition Table 21 6 shows what the interaction between the TWI controller...

Page 761: ...ode operation As an example programming the value 0x0201 enables master mode operation generates a 7 bit address sets the direction to master receive uses standard mode timing and receives 8 data byte...

Page 762: ...rvice routine development Transmit Receive Repeated Start Sequence Figure 21 11 illustrates a repeated start data transmit followed by a data receive sequence The tasks performed at each interrupt are...

Page 763: ...the following bits of TWI_MASTER_CTRL register Clear RSTART if this is the last transfer Re program DCNT with the desired number of bytes to receive TWISERR interrupt This interrupt is generated due t...

Page 764: ...er begins TWIMCOMP interrupt This interrupt has occurred due to the completion of the data receive transfer At this time the data transmit transfer begins The TWIDCNT field should be set to reflect th...

Page 765: ...nerate a flexible core clock Allows changes to the output clock during runtime RESETOUT pin can be used for boot handshake or as a debug aid Resetting the PLL is possible without performing a new powe...

Page 766: ...which performance flexibility and control of power dissipation are key features This broad range of applications requires a range of frequencies for the clock generation circuitry The input clock may...

Page 767: ...ct data sheet PLL Input Clock If an external clock oscillator is used it should NOT drive the CLKIN pin when the processor is not powered The clock must be driven immediately after power up otherwise...

Page 768: ...g up the clock can be selected through software control For information on the internal clock to CLKIN frequency ratios supported by the various processors see the product specific data sheet PLLM Sof...

Page 769: ...ion for the PLL cir cuitry Therefore the core needs to wait a specific settling time in bypass mode before it can be released for further activities typically 4096 CLKIN cycles Output Clock Generator...

Page 770: ...nged any time and new division ratios are implemented on the fly IOP Clock PCLK The peripheral clock is derived from the core clock with a fixed post divi sor of 2 This clock is the master clock for a...

Page 771: ...he core runs at CLKIN speed Once the PLL has settled into the new VCO frequency which may take 4096 CLKIN cycles the PLLBP bit may be cleared to release the core from bypass mode For more information...

Page 772: ...ny time for example after power up or during operation Clocking Golden Rules The five rules below should be followed to ensure proper processor operation 1 After power up the CLK_CFG pins should not e...

Page 773: ...execute or begin the boot process A delayed core reset signal RESETOUT is triggered by a 12 bit counter after RESET is transitioned from low to high approximately 400 s for minimum CLKIN The delay ci...

Page 774: ...be disabled using the PMCTL1 register The PMCTL1 register allow programs to disable the clock source to a partic ular processor peripheral for example the external port to further conserve power Prog...

Page 775: ...t used the DSDCTL bit can be disabled to stop the clock and reduce power dissipation The DSDCTL bit must be set 1 in products without the SDRAM interface to reduce power consumption Set this bit as ea...

Page 776: ...nd its digital PLL from the S PDIF receiver By default the S PDIF receiver is enabled If not required set the DIR_RESET bit 1 to disable the digital PLL which may produce unwanted switching noise if e...

Page 777: ...is required to release the processor from IDLE Don t leave input pins floating In some cases leakage draws cur rent in the region of milliamps For more information consult the product specific data sh...

Page 778: ...2 Select the PLLD divider by setting the PLLD bits 6 7 in the PMCTL register and enable the DIVEN bit 3 Wait 15 CCLK cycles During this time the new divisor ratios are picked up on the fly and the cl...

Page 779: ...t in bypass mode until the PLL locks 4096 CLKIN cycles 4 Take the PLL out of bypass mode by clearing 0 the bypass bit Clear the DIVEN bit while taking the PLL out of bypass mode 5 Wait 15 core cycles...

Page 780: ...hould be cleared while placing the PLL in bypass mode waiting_loop r0 4096 wait for PLL to lock at new rate requirement for VCO change lcntr r0 do pllwait until lce pllwait nop ustat2 dm PMCTL Reading...

Page 781: ...returns the DIVEN bit value as zero The DIVEN bit should be cleared while taking the PLL out of bypass mode bit clr ustat2 PLLBP take PLL out of Bypass PLL is now at new CCLK dm PMCTL ustat2 bit set u...

Page 782: ...HARC Processor Hardware Reference Listing 22 5 Back to Back Bypass ustat3 dm PMCTL bit clr ustat3 PLLBP dm PMCTL ustat3 PLLBP is cleared nop nop nop nop ustat4 dm PMCTL bit set ustat4 PLLBP dm PMCTL u...

Page 783: ...Processor Booting on page 23 7 Pin Multiplexing on page 23 28 High Frequency Design on page 23 33 System Components on page 23 40 Before proceeding with this chapter it is recommended that you become...

Page 784: ...e Reset Control Register SYSCTL Controls the software reset mechanism Running Reset Control Register RUNRSTCTL Controls the function ality of the RESETOUT pin as running reset input EP Control Registe...

Page 785: ...ter and gives an overview of the different reset methods Hardware Reset All members of the SHARC processor family support the hardware reset controlled with the RESET pin The deassertion of this pin...

Page 786: ...t2 No No No 1 Internal memory array does not have reset Only power up down can change array contents or direct read write by the core or DMA However if data exists in shadow FIFOs then that data is re...

Page 787: ...gram memory from the reset interrupt vector table Running reset allows programs to Execute self modifying code that has previously overwritten exist ing code in internal memory Activate an external wa...

Page 788: ...n during and after RESET The processor is actively driving this pin as an output If the system uses an external host or micro controller to control running reset ensure that the external device waits...

Page 789: ...PI of a SHARC as shown in Figure 23 2 In this case the host implements the SPI protocol on the port pins Processor Booting When a processor is initially powered up its internal SRAM is undefined Befor...

Page 790: ...kernel load the core is put in IDLE After the interrupt is generated the core jumps to reset location and starts kernel execution External Port Booting The ADSP 214xx processors allow booting through...

Page 791: ...sters are initialized to the values listed in Table 23 4 In this configuration the loader kernel is read via DMA from the FLASH If the application needs to speed up read accesses programs should chang...

Page 792: ...B0SD No SDRAM bank 0 cleared 0 1 B1SD No SDRAM bank 1 cleared 0 2 B2SD No SDRAM bank 2 cleared 0 3 B3SD No SDRAM bank 3 cleared 0 5 4 EPBR Rotating priority core vs DMA 11 7 6 DMAPR Rotating priority...

Page 793: ...cleared 0 21 CHS Status cleared 0 22 TLS Status cleared 0 23 WBS Status cleared 0 24 EXTS External access pending set 1 25 DIRS Status cleared 0 Table 23 5 Parameter Initialization for External Port B...

Page 794: ...ormation see DPI Default Routing on page 9 31 Master Boot Mode In master boot mode the processor initiates the booting operation by 1 Activating the SPICLK signal and asserting the SPI_FLG0_O signal t...

Page 795: ...F Cleared 0 LSB first WL 10 32 bit SPI receive shift register word length DMISO Cleared 0 MISO enabled SENDZ Set 1 Send zeros SPIRCV Set 1 Receive DMA enabled CLKPL Set 1 Active low SPI clock CPHASE S...

Page 796: ...ot programmed to 0xA5 the master boot transfer is aborted The transfer continues until 384 x 32 bit words have been transferred which may correspond to the loader program just as in the slave boot mod...

Page 797: ...perly the SPI DMA initially loads a DMA count of 0x180 384 32 bit words which is equivalent to 0x100 256 48 bit words Note that for SPI slave boot SPIDS should only be asserted after RESETOUT has deas...

Page 798: ...t the DMA parameter registers are initialized to the values listed in Table 23 10 Table 23 9 SPICTL Slave Boot Settings 0x4D22 Bit Setting Comment SPIEN Set 1 SPI enabled SPIMS Cleared 0 Slave device...

Page 799: ...words shift into the 32 bit receive shift reg ister RXSR before a DMA transfer to internal memory occurs for 16 bit SPI devices For 8 bit SPI devices four words shift into the 32 bit receive shift reg...

Page 800: ...ons exe cuted at PM addresses PMaddr0 and PMaddr1 The 32 bit word is shifted to internal program memory during the 256 word kernel load The following example shows a 48 bit instruction executed PMaddr...

Page 801: ...0x112233445566 PMaddr1 0x7788AABBCCDD The 16 bit SPI host packs or prearranges the data as The initial boot of the 256 word loader kernel requires a 16 bit host to transmit 768 16 bit words Two packe...

Page 802: ...nstruction executed PMaddr0 0x112233445566 PMaddr1 0x7788AABBCCDD The 8 bit SPI host packs or prearranges the data as The initial boot of the 256 word loader kernel requires an 8 bit host to transmit...

Page 803: ...link port clock LCLK0 Boot data is shifted in 8 bits every clock cycle through the LDAT0x pins The received data streams of 4 x 8 bit is packed by the 2 deep RXLP0 buffer into 32 bit words least signi...

Page 804: ...AN Receive operation cleared 0 7 BHD Buffer hang disabled cleared 0 8 LTRQ_MSK LP transmit request mask cleared 0 9 LRRQ_MSK LP receive request mask cleared 0 10 DMACH_IRPT_MSK LP DMA channel interrup...

Page 805: ...IVT 256 words The complete time for booting can be estimated by adding all 5 timing windows Loading Kernel and Loading IVT both have the same size how ever the default access time wait states for the...

Page 806: ...M It can be changed to the internal RAM by setting IIVT bit of SYSCTL register Code always executes from internal ROM Non Secured ROM hardware security switch 0 In this mode BOOTCFG2 0 pins select the...

Page 807: ...o the RUNRSTCTL register 3 Wait at least 5 CCLK cycles to ensure that the pin is configured as an input 4 When the processor is ready to accept the running reset it signals the host over the command i...

Page 808: ...Once the kernel is executed initialization of some core and exter nal peripheral registers and such as AMI or SDRAM the kernel prepares a DMA for further data 2 After this the DMA starts and the core...

Page 809: ...cated kernel to the dedicated boot type for example SPI kernel and SPI boot type in the elf loader property page If this is not done the RTI instruction in Loading the Application s Interrupt Vector T...

Page 810: ...rocessors provide extensive functionality using a low pin count reducing system cost They do this through extensive use of pin multiplexing The following sections provide information on this feature A...

Page 811: ...trol register Backward Compatibility The FLAG IRQ 0 1 2 3 pins retain their old functionality and program ming No changes are required for old programs The select lines for multiplexes are controlled...

Page 812: ...can be mapped to any of the AMI pins PDAP data control can be completely moved to AMI pins instead of DAI pins PDAP PWM signals can be mapped only to the upper bits of the AMI address pins FLAGS PWM c...

Page 813: ...t or DPI pins operates in parallel Note that For FLAG3 0 In output mode if the same flag is mapped to both external port pins and FLAG3 0 pins then the output is driven to both pins In input mode if t...

Page 814: ...FLAGS11 8 PWM15 12 3 0 15 12 11 8 7 4 DPI PINS ADDR23 8 ADDR7 0 DATA7 0 ADDR7 0 FLAGS15 4 M U X M U X M U X M U X M U X M U X M U X FLAG3 0 PINS FLAG0_PIN IRQ0 FLAG0 FLAG1_PIN FLAG2_PIN FLAG3_PIN IRQ1...

Page 815: ...or reflections The following sections describe why these circuits are needed and their effect on input signals Clock Input Specifications and Jitter The clock input signal must be free of ringing and...

Page 816: ...the hysteresis is approximately 100 mV The hysteresis is intended to prevent multiple triggering of signals that are allowed to rise slowly as might be expected for example on a reset line with a del...

Page 817: ...ups or pull downs are used Connections directly to power or ground can be used only if the pins can be guaranteed to never be con figured as outputs Memory Select Pins When the multiplexed memory sele...

Page 818: ...be recognized in the current cycle or during the next cycle To ensure recognition of an asynchronous input it must be asserted for at least one PCLK cycle plus setup and hold time except for RESET whi...

Page 819: ...digital signals near or under the clock sources Other Recommendations and Suggestions Use more than one ground plane on the PCB to reduce crosstalk Be sure to use lots of vias between the ground plan...

Page 820: ...lder pads Sur face mount capacitors are recommended because of their lower series inductances ESL and higher series resonant frequencies Connect the power and ground planes to the processor s power su...

Page 821: ...ed measurements be sure to use a bayonet type or similarly short 0 5 inch ground clip attached to the tip of the oscil loscope probe The probe should be a low capacitance active probe with 1 pF or les...

Page 822: ...Signal Propagation Advanced Black Magic Johnson Gra ham Prentice Hall Inc ISBN 0 13 084408 X System Components This section provides some recommendations for other components to use when designing a s...

Page 823: ...that is released once the power supplies and internal clock cir cuits have stabilized The RESET signal should not only offer a suitable delay but it should also have a clean monotonic edge Analog Dev...

Page 824: ...es power on RESET and optional manual RESET It allows designers to create a more complete supervisory circuit that monitors the supply voltage Monitoring the supply voltage allows the system to initia...

Page 825: ...and is automatically performed by the processor after power up or after a software reset Boot Kernel The boot kernel is an executable file which schedules the entire boot pro cess The temporary locat...

Page 826: ...peripheral used See Proces sor Booting on page 23 7 Boot Modes The boot mode is identified by the BOOT_CFG2 0 pins that are used in the boot process No Boot Mode In legacy mode the processor does not...

Page 827: ...anagement Registers on page A 4 ADSP 2146x External Port Registers on page A 18 DAI Signal Routing Unit Registers on page A 118 Peripherals Routed Through the DAI on page A 150 DPI Signal Routing Unit...

Page 828: ...ocessor core registers The register names for I O processor registers are not part of the proces sor s assembly syntax To ease access to these registers programs should use the header file containing...

Page 829: ...control register bits are read write RW and sta tus register bits are read only RO In exceptional cases bit types are shown in the Bit column in parenthesis where for example a RO bit is used in a con...

Page 830: ...tion see Pin Multiplexing on page 23 28 Bit descriptions for this register are shown in Figure A 1 and described in Table A 2 WO Write Only WO bits are used primarily in control status register to tri...

Page 831: ...ated to interrupt request IRQ2 19 TMREXPEN Flag Timer Expired Mode 0 Flag3 pin is a general purpose I O pin Permits core writes 1 Flag3 pin output is timer expired signal TMREXP 20 MSEN Memory Select...

Page 832: ...ADSP 2147x and ADSP 2148x 25 PWM1EN Pulse Width Modulation Select When set 1 enables PWM7 4 For more information see Pin Multiplexing on page 23 28 26 PWM2EN Pulse Width Modulation Select When set 1...

Page 833: ...tput values PLL bypass mode and clock enabling control for peripherals see Table A 3 on page A 8 This register also contains status bits which keep track of the status of the CLK_CFG pins read only Th...

Page 834: ...16 8 INDIV PLL Input Clock Pre Divider 0 Divide by 1 1 Divide by 2 9 WO DIVEN Output Clock Divider Enable Enables the post divider settings 0 Do not load PLLD 1 Load PLLD When the PLL is programmed us...

Page 835: ...pins After reset both CLK_CFG pins define the CLKIN to core clock ratio This ratio can be changed with the PLLM and PLLD bits CRAT CLK_CFG 1 0 0 CLK_CFG 1 0 00 6 1 ratio 1 CLK_CFG 1 0 01 32 1 ratio 2...

Page 836: ...CP 0 MTM is in normal mode 1 Shutdown clock to MTM LP0OFF ACCOFF Accelerator Clocks Shutdown ACCSEL 18 17 Accelerator Select UART0POFF UART Clock Shutdown MLBOFF MLB Clock Shutdown LP0 Clock Shutdown...

Page 837: ...mode 1 Shutdown clock to SPORTs 8 SP45OFF Shutdown Clock to SPORT 4 5 0 SPORTs in normal mode 1 Shutdown clock to SPORTs 9 SP67OFF Shutdown Clock to SPORT 6 7 0 SPORTs in normal mode 1 Shutdown clock...

Page 838: ...trol phase lock loop PLL multiplier and divider both input and output values PLL bypass mode and clock enabling control for peripherals see Table A 5 This register also contains status bits which keep...

Page 839: ...32x 10 010000 16x 11 001000 8x 7 6 PLLD PLL Divider Output Clock Post Divider 00 clock divider 2 01 clock divider 4 10 clock divider 8 11 clock divider 16 8 INDIV PLL Input Clock Pre Divider 0 Divide...

Page 840: ...ly used for test purposes 14 13 Reserved 15 PLLBP PLL Configuration Ratio CLK_CFG1 0 pins After reset both CLK_CFG 1 0 pins defines the CLKIN to core clock ratio This ratio can be changed with the PLL...

Page 841: ...gister RTCOFF ACCOFF Accelerator Clocks Shutdown ACCSEL 18 17 Accelerator Select UART0POFF UART Clock Shutdown MLBOFF MLB Clock Shutdown RTC Clock Shutdown TWIOFF TWI Clock Shutdown PWMOFF PWM Clock S...

Page 842: ...wn Clock to DAI Shutdown clock to DAI related peripherals SRU SRC S PDIF PCG IDP PDAP 0 DAI is in normal mode 1 Shutdown clock to DAI 5 EPOFF Shutdown Clock to External Port 0 External port is in norm...

Page 843: ...rmal mode 1 Shutdown clock to RTC 15 14 Reserved 16 ACCOFF Shutdown Clock to Accelerator 0 Accelerator is in normal mode 1 Shutdown clock to accelerator 18 17 ACCSEL Accelerator Select 00 Select FIR 0...

Page 844: ...ace AMI the DDR2 and SDRAM controllers and the shared memory interface The external port control register can be programmed to arbi trate the accesses between the processor core and DMA and between di...

Page 845: ...2 Non DDR2 1 Bank 2 DDR2 3 B3SD Select Bank 3 DDR2 DRAM 0 Bank 3 Non DDR2 1 Bank 3 DDR2 B0SD Bank 0 DDR2 DRAM B1SD Bank 1 DDR2 DRAM B2SD Bank 2 DDR2 DRAM B3SD Bank 3 DDR2 DRAM DMAPR 7 6 DMA Channel Pr...

Page 846: ...ort DMA Channel Priority 00 Reserved 01 EP DMA channel 1 high priority 10 EP DMA channel 0 high priority 11 Rotating priority default 10 8 FRZDMA Arbitration Freezing Length for DMA 000 No Freezing 00...

Page 847: ...e size of DDR21 110 111 Reserved 31 19 Reserved 1 The EPCTL register automatically reads the DDR2CTL0 page size setting DDR2CAW pro grams just need to program the EPCTL for selecting page size freeze...

Page 848: ...Significant Word First Applicable only with packing disabled PKDIS 0 0 1st 8 bit word read write occupies the least significant position in the 32 bit packed word 1 1st 8 bit word read write occupies...

Page 849: ...010 2 cycles 011 3 cycles 100 4 cycles 101 5 cycles 110 6 cycles 111 7 cycles 17 FLSH AMI Buffer Flush Write Only 0 Buffer holds the data 1 Flush the buffer 20 18 RHC Read Hold Cycle at the End of Re...

Page 850: ...these registers with values that are in the operating range of the DDR2 used Values in the reserved fields in these registers must be maintained according to the DDR2 specification Writing to reserve...

Page 851: ...e DDR2SRF Force MR Register Write DDR2ORF Self Refresh Entry Mode Disable Auto Refresh Mode FAR Force Auto Refresh FEMR FPC SREF_EXIT Self Refresh Exit Force Precharge DIS_DDR2CTL FDLLCAL Force On chi...

Page 852: ...ad power consump tion 1 DIS_DDR2CLK1 Disable DDR2 Clock 1 Used to disable the 2nd output clock of the controller By default both output clocks are driven 0 Activate 1 Disable 3 2 DDR2BC Bank Count 4 o...

Page 853: ...ects how the data are stored in the DDR2 memory 0 Page interleaving map consecutive pages different banks 1 Bank interleaving map consecutive banks 15 WO DDR2PSS Power Up Sequence Start The power up s...

Page 854: ...is also set otherwise the DDR2 may crash 0 No effect 1 Force auto refresh 21 WO FPC Force Precharge All This bit allows programs to explicitly trig ger a PREA command 0 No effect 1 Force precharge 22...

Page 855: ...d optimization 1 Enable read optimization 31 28 DDR2MODIFY Read Modifier In Optimization Mode 0000 Modifier 0 0001 Modifier 1 1111 Modifier 15 Note that these bits only are used in SISD mode Figure A...

Page 856: ...Time Note that for 8 banked devices the timing spec becomes tRP 1tCK 0000 Reserved 0001 1 clock cycle 0010 2 clock cycles 1111 15 clock cycles 11 9 DDR2TWTR Write to Read Delay 000 Reserved 001 1 clo...

Page 857: ...changed while DDR2 inter face is active Also whenever this register contents are changed a initialization sequence must be executed to reflect this register con tents in to the DDR2 mode register 24...

Page 858: ...cy 000 Reserved 001 Reserved 010 2 clock cycles 111 7 clock cycles 7 Reserved 8 DDR2DLLRST DLL Reset 0 Normal 1 Reset 11 9 DDR2TWR Write Recovery Time 000 Reserved 001 2 clock cycle 010 3 clock cycles...

Page 859: ...tion sequence This register s contents should not be changed while DDR2 inter face is active Also whenever this register s contents are changed an initialization sequence must be executed to reflect t...

Page 860: ...The basic rule for additive latency is defined as AL tRCDmin 1 Example tRCD is 4 cycles then AL 3 0 If AL 4 tRCD is increased by 1 cycle increasing overall latency 6 2 DDR2ODT On Die Termination Valu...

Page 861: ...inter face is active Also whenever this register contents are changed an initialization sequence must be executed to reflect this register con tents in to the DDR2 extended mode register 3 DDR2 Contr...

Page 862: ...igure A 13 and Table A 17 provides a flexible mechanism for specifying the auto refresh timing The delay in number of DDR2CLK cycles desired between consecutive refresh counter time outs must be writt...

Page 863: ...tions RW Bit Name Description 13 0 RDIV RDIV value defines the number of clock cycles between two refresh commands 20 14 Reserved 28 21 tRFC Row refresh interval minimum refresh interval in clock cycl...

Page 864: ...reset 4 DDR2MSE Access Error 0 No Error 1 An access request to DDR2 lost because controller external pins are in disabled state DIS_DDCTL set Write a 0 to clear this bit if set sticky bit 5 Reserved...

Page 865: ...1 in open state xxxxxx0x Internal bank 1 in precharge state 1xxxxxxx Internal bank 7 in open state 0xxxxxxx Internal bank 7 in precharge state 15 8 External Bank 1 Status External Bank 0 Active Prech...

Page 866: ...charge state 1xxxxxxx Internal bank 7 in open state 0xxxxxxx Internal bank 7 in precharge state 31 24 External Bank 3 Status External Bank 0 Active Precharge State xxxxxxx1 Internal bank 0 in open sta...

Page 867: ...ogic only including the 90 degree DQS shifters 0 No effect 1 Reset DLL0 control logic 10 RESETDAT Reset Data Capture Logic Active high when active it resets the data capture logic only including P and...

Page 868: ...gic Active high when active it resets the data capture logic only including P and N buffers 0 No effect 1 Reset DLL1 reset capture logic 11 RESETCAL Reset DQS Phase Calibration Logic Active high when...

Page 869: ...TL0 Register Bit Descriptions RW Bit Name Description 8 0 Reserved 9 DATA_PWD Data Pad Receiver Power Down 0 Normal mode 1 Power down mode 18 10 Reserved 19 DQS_PWD DQS Pad Receiver Power Down 0 Norma...

Page 870: ...T and Address pad control Figure A 19 DDR2PADCTL1 Register Table A 24 DDR2PADCTL1 Register Bit Descriptions RW Bit Name Description 8 0 Reserved 9 ADDR_PWD Address Pad Receiver Power Down 0 Normal mod...

Page 871: ...te the accesses between the processor core and DMA and between different DMA channels These registers are shown in Figure A 20 and described in Table A 25 Figure A 20 EPCTL Register B0SD Bank 0 SDRAM...

Page 872: ...hat the MS3 pin is multiplexed 5 4 EPBR External Port Bus Priority 00 Reserved 01 DMA has high priority 10 Core has high priority 11 Rotating priority default 7 6 DMAPR External Port Bus Priority 00 P...

Page 873: ...32 Accesses 101 Page size SDRAM only1 110 111 Reserved 18 15 DATEN EP Data Mask Enable In no pack mode of the SDRAM AMI memory controller masks those bits of the data lane DL with zeros The data lane...

Page 874: ...r Any access made to a bank whose AMIEN bit is not set occurs at WS 2 and 8 bit mode without any hold idle cycles In any case this access occurs without the bank select and is a void access Moreover t...

Page 875: ...sampled after the wait state value is programmed 10 6 WS Wait States 00000 Reserved wait state value of 32 if used 00001 wait state 1 only if ACK input used 00010 wait state 2 11111 Wait state 31 Wait...

Page 876: ...e Idle cycles are also required to provide time for a slave in one bank to three state its ACK driver before the slave in the next bank enables its ACK driver 17 WO AMIFLSH AMI Buffer Flush Flushes bo...

Page 877: ...s all programmable parame ters associated with the SDRAM access timing and configuration This 32 bit register is shown in Figure A 23 and described in Table A 28 Figure A 22 AMISTAT Register Table A 2...

Page 878: ...uto Refresh FPC Force Precharge STDRCD 26 24 Force LMR Address Map Mode PGSZ 128 Page size is 128 bits Force Auto Load Mode Register SDCL 2 0 SDSRF SDRAM Self Refresh Enable SDPSS SDRAM Power up Seque...

Page 879: ...3 DSDCLK1 Disable Clock SDCLK1 For ADSP 2148x only 1 No effect 0 Disable SDCLK1 7 4 SDTRAS tRAS Specification Row Active Open Delay is 1 15 SDCLK cycles Based on the system clock frequency and the ti...

Page 880: ...ut the SDRAM into self refresh mode Any access to the enabled SDRAM bank causes the SDC to trigger a self refresh exit command 16 X16DE SDRAM External Data Path Width This bit should always be set 18...

Page 881: ...TRCD SDRAM tRCD Specification RAS to CAS Delay is 1 7 SDCLK cycles Based on the system clock frequency and the timing specifica tions of the SDRAM used Programmed parameters apply to all four banks in...

Page 882: ...elf refresh mode SDCKE pin low 2 SDPUA SDC Power Up Active If set controller is in power up mode 0 Non power up mode SDPSS bit cleared in SDCTL 1 Power up mode SDPSS bit set in SDCTL 3 SDRS SDC Reset...

Page 883: ...precharge state xx1x Internal bank 1 in open state xx0x Internal bank 1 in precharge state 1xxx Internal bank 7 in open state 0xxx Internal bank 7 in precharge state 15 8 External Bank 1 Status Extern...

Page 884: ...bit see SDRAM Read Optimization on page 3 40 23 16 External Bank 2 Status External Bank 0 Active Precharge State xxx1 Internal bank 0 in open state xxx0 Internal bank 0 in precharge state xx1x Intern...

Page 885: ...SDROPT SDRAM Read Optimization If set 1 enables read optimization to improve read throughput for core or external port DMA access 0 Disabled 1 Enabled Default setting is 1 20 17 SDMODIFY SDRAM Read M...

Page 886: ...Loading Status DMAS DMA Transfer Status INTIRT DMA Direction DMA Enable CHEN Chaining Enable TRAN DMA FIFO Status DIRS DLEN Delay Line DMA Enable CBEN Circular Buffering Enable DFLSH Flush DMA FIFO CH...

Page 887: ...1 Delay line DMA enabled 4 CBEN Circular Buffering Enable 0 Disables circular buffering with delay line DMA 1 Enables circular buffering with delay line DMA Circular buffering can be used with normal...

Page 888: ...16 RO DFS DMA FIFO Status 00 FIFO Empty 01 FIFO Partially Full 11 FIFO Full 10 Reserved 19 18 Reserved 20 RO DMAS DMA Transfer Status 0 DMA idle 1 DMA in progress 21 RO CHS DMA Chaining Status 0 DMA...

Page 889: ...ol registers Control Register LCTLx Figure A 28 and Table A 33 describe the bit fields within this register 25 RO DIRS DMA Transfer Direction Status 0 DMA direction is external reads 1 DMA direction i...

Page 890: ...link buffer x LBUFx 3 LTRAN Link Buffer Transfer Direction This bit selects the transfer direction transmit if set 1 receive if cleared 0 for link buffer x LBUFx 6 4 Reserved 7 LP_BHD Buffer Hang Disa...

Page 891: ...nal Transfer Done Interrupt Mask Valid for core and DMA accesses If set interrupt is generated when the FIFO is empty Note if bit 10 is also set for DMA two interrupts are generated one for DMA count...

Page 892: ...ption 0 ROC LTRQ Link Port Transmit Request Status 1 ROC LRRQ Link Port Receive Request Status 2 ROC DMACH_IRPT DMA Channel Count Interrupt 3 ROC LPIT Link Port Invalid Transmit Interrupt 4 ROC EXTTXF...

Page 893: ...register the traditional read modify write operations to disable the PWM group have changed The action is to directly write this simplifies the enable disable of the PWM groups and can be done with fe...

Page 894: ...isable bits Figure A 31 PWMGCTL Register Table A 35 PWMGCTL Register Bit Descriptions RW Bit Name Function 0 2 4 6 PWM_ENx0 PWM Group x Enable 1 3 5 7 PWM_DISx PWM Group x Disable PWM_DIS3 PWM_DIS1 PW...

Page 895: ...from individual groups 8 10 12 14 PWM_SYNCENx PWM Group x Enable 9 11 13 15 PWM_SYNCDISx PWM Group xDisable Table A 36 PWMGSTAT Register Bit Descriptions W1C Bit Name Function 0 PWM_STAT0 PWM Group 0...

Page 896: ...Paired mode The PWM generates the complementary signal from the high side output xL xH 2 PWM_UPDATE Update Mode 0 Single update mode The duty cycle values are programmable only once per PWM period Th...

Page 897: ...Status Set during center aligned mode in the sec ond half of each PWM period Allows programs to determine the particular half cycle first or second during PWM interrupt ser vice routine if required 0...

Page 898: ...l A High Disable Enables or disables the channel A output signal 0 Enable 1 Disable 3 PWM_AL Channel A Low Disable Enables or disables the channel A output signal 0 Enable 1 Disable 4 BHBL_XOVR Crosso...

Page 899: ...pairs of PWM signals 2 PWM_POL1AH Channel AH Polarity 1 0 Channel AH polarity 0 1 Channel AH polarity 1 default 3 PWM_POL0AH Channel AH Polarity 0 0 Channel AHpolarity 0 1 Channel AH polarity 1 defau...

Page 900: ...ning off one PWM signal and turning on its complementary signal Debug Status Registers PWMDBGx These 16 bit registers aid in software debug activities FFT Accelerator Registers The following sections...

Page 901: ...scription 0 FFT_RST Reset Accelerator Setting this bit puts the accelerator into reset mode Explicit clearing of this bit is necessary to take the accelerator out of reset 0 Normal operation 1 Reset 1...

Page 902: ...packing 6 FFT_DBG Debug Mode Enable 0 Disable 1 Enable 31 7 Reserved Figure A 34 FFTCTL2 Register Table A 42 FFTCTL1 Register Bit Descriptions RW Cont d Bits Name Description VDIM 11 7 FFT_RPT FFT_CPA...

Page 903: ...Word Input Packing for 512 Words 0 No packing first all reals then all imag are received by the accelerator 1 Complex numbers are packed Real Imag For 256 words this bit is always set 2 FFT_CPACKOUT C...

Page 904: ...s information Table A 44 FFT_MACSTAT Register Bit Descriptions ROC Bits Name Description 0 FFT_NAN Bits 3 0 follow the IEEE STD for floating point num bers 1 FFT_DENORM 2 FFT_OVR 3 FFT_UDR 31 4 Reserv...

Page 905: ...ribe the registers used to program and debug the FIR accelerator Global Control Register FIRCTL1 The FIRCTL1 register shown in Figure A 35 and described in Table A 47 is used to configure the global p...

Page 906: ...AI Channel Auto Iterate 0 Processing stops once all channels are over 1 Moves to first channel and continues processing in a loop when all channels are over 10 Reserved FIR_TC Two s Complement Format...

Page 907: ...default 1 Interrupt is generated after each channel is done 12 FIR_FXD Fixed Point Accelerator Select 0 32 bit IEEE floating point 1 32 bit fixed point 13 FIR_TC Two s Complement Format Input Select F...

Page 908: ...sample based operation and the maximum win dow size is 1024 24 Reserved 27 25 FIR_RATIO UP DOWN Sampling Ratio Sampling Ratio RATIO 1 28 Reserved 29 FIR_SRCEN Sample Rate Conversion Enable 0 Disabled...

Page 909: ...lt Infinity Set if multiplier 0 results is infinity 2 FIR_MACMINV0 Multiply Invalid Set if multiplier 0 multiply operation is invalid 3 FIR_MACARZ0 Adder Result Zero Set if a adder 0 results is zero 4...

Page 910: ...MINV2 Multiply Invalid Set if multiplier 2 multiply operation is invalid 15 FIR_MACARZ2 Adder Result Zero Set if a adder 2 results is zero 16 FIR_MACARI2 Adder Result Infinity Set if adder 2 results i...

Page 911: ...MACLD Coefficient Loading 2 FIR_DMADLD Data Preload 3 FIR_DMAPPGS MAC Processing in Progress 4 FIR_DMAWRBK Writing Back the Updated Index Registers 5 ROC FIR_DMAWDONE Processing of Current Channel Don...

Page 912: ...n the TDM slot Zero indicates the last slot 13 12 CURITER Current MAC Iteration Current MAC iteration in multi iteration mode Zero indicates the final iteration 31 14 Reserved Figure A 39 FIRDEBUGCTL...

Page 913: ...GCTL Register Bit Descriptions RW Bits Name 0 FIR_DBGMODE Debug Mode Enable 0 Disable 1 Enable For local memory access the FIRCTL1 register can be cleared 1 FIR_HLD Hold Or Single Step The function of...

Page 914: ...ng stops once all channels are over 1 Moves to first channel and continues processing in a loop when all channels are over 10 IIR_SS Save State Stores the Dk registers settings into local mem ory IIR_...

Page 915: ...t Floating Point Format Select 0 32 bit IEEE floating point 1 40 bit IEEE floating point 13 Reserved 16 14 IIR_RND Rounding Mode Select for Floating Point Mode 000 IEEE round to nearest even 001 IEEE...

Page 916: ...1 IIRCTL2 Register Table A 53 IIRCTL2 Register Bit Descriptions RW Bits Name Description 3 0 IIR_NBIQUADS Number of Biquads Programmable between 0 11 Number of Biquads BIQUADS 1 13 4 Reserved 23 14 II...

Page 917: ...in this register are read only Figure A 42 IIRMACSTAT Register Table A 54 IIRMACSTAT Register Bit Descriptions RO Bits Name Description 0 IIR_MRZ Multiplier Result Zero Set if multiplier results is z...

Page 918: ...of Current Channel Done Sticky cleared on register read 6 ROC IIR_DMAACDONE All Channels Done Sticky cleared on register read 11 7 IIR_DMACURCHNL Current Channel Channel that is being processed in th...

Page 919: ...Enable For local memory access the IIRCTL1 register can be cleared 1 IIR_HLD Hold or Single Step The function of this bit is based on the IIR_DBGMEM bit setting For IIR_DBGMEM 0 1 Single step For IIR_...

Page 920: ...ice enable disable clock rate lock status and addressing 5 IIR_ADRINC Address Auto Increment If this bit is set the address register auto increments on IIRDBGWRDATA_H IIRDBGWRDATA_L writes and IIRDBGR...

Page 921: ...O MRS MLB Software Reset When set resets the MLB physical and link layer logic Hardware clears this bit automatically 24 MHRE MLB Hardware Reset Enable Enables hardware to automatically reset the MLB...

Page 922: ...frame to prevent the current frame status from being lost 29 28 MCS MLB Clock Select 00 256Fs supports 8 quadlets per frame 01 512Fs supports 16 quadlets per frame 10 1024Fs supports 32 quadlets per...

Page 923: ...m command 1 SDNL System Detects Network Lock When set indicates the MLB device has received Most lock system command 2 SDNU System Detects Network Unlock When set indicates the MLB device has received...

Page 924: ...nd When set this bit masks system inter rupts for Mlb Reset system command 2 SMNU System Masks Network Unlock When set this bit masks system inter rupts for the MOST_unlock system command 1 SMNL Syste...

Page 925: ...bit offset configured using the BCA bits in the MLB_CCBCRx register The base address registers and offset registers use round robin arbitration to determine which logical channel is granted access to...

Page 926: ...holds the base address of the system memory buffers of all asynchronous channels in the device Table A 62 MLB_SBCR Register Bit Descriptions RW Bit Name Description 4 0 STBA Synchronous transmit base...

Page 927: ...ers The MLB controller supports up to 31 logical channels Therefore the variable in the register names is valid for x 0 30 This section lists all different control and status registers related to the...

Page 928: ...A 66 provide information for for asynchronous and control channels and Figure A 49 and Table A 67 provide informa tion for for synchronous channels Figure A 48 MLB_CECRx Register Asynch and Control Ch...

Page 929: ...indepen dent of and in addition to other service requests generated via the standard buffer threshold mechanism In DMA mode these bits are reserved 15 13 Reserved 16 MASK0 Mask Protocol Error When set...

Page 930: ...pong DMA mode default 01 Circular buffering DMA 10 I O mode enable 11 Reserved 27 PCE Packet Count Enable Enable the Rx packet counter This bit is valid for asynchronous and control Rx channels in I...

Page 931: ...11 0x01FE 12 8 FSPC Frame Synchronization Physical Channel Count Defines the num ber of physical channels expected to match this logical channel s channel address each MLB frame 14 13 Reserved 15 FSCD...

Page 932: ...MASK3 I O Masks Transmit Service Request When set masks Tx channel ser vice request interrupts for this logical channel 19 MASK3 DMA Mask Buffer Start When set masks buffer start channel interrupts fo...

Page 933: ...t 00 Synchronous default 01 Reserved 10 Asynchronous 11 Control 30 CTRAN Channel x Transmit Select 0 Receive default 1 Transmit 31 CE Channel x Enable 0 Channel x disabled default 1 Enabled Table A 67...

Page 934: ...DY Next Buffer Ready 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 BF Channel x Buffer Empty Channel x Buffer Full STS 1 Current Buffer Detect Break STS 2 Recei...

Page 935: ...re Receive service requests are issued if the number of free quadlets in the local channel buffer is less than or equal to LCBCRn TH 9 0 The setting of this bit generates a maskable channel interrupt...

Page 936: ...tem software This interrupt can be used by sys tem software to detect when it has encountered the beginning of an aborted packet This bit is valid for asynchronous and control RX channels only 8 STS8...

Page 937: ...in I O mode 11 STS11 DMA Previous Buffer Start Indicates the first quadlet of the Previous Buffer has been successfully transmitted or received The setting of this bit generates a maskable channel in...

Page 938: ...ad write Local Buffer Configuration Registers MLB_LCBCRx These registers described in Table A 71 allow software to optimize the use of the local channel buffer memory These registers should only be wr...

Page 939: ...of 8 words 0x001E start address offset of 120 words 0x001F to 0x1FFF Reserved 21 13 BD Buffer Depth Defines the depth in quadlets 4 1 of the local channel buffer for the logical channel x 0x000 depth...

Page 940: ...register WDTUNLOCK Attempts by the core to write to WDTCTL without an unlock command causes the WDT to expire and reset the sys tem This condition is captured in the watchdog exception field WDERR Wri...

Page 941: ...imes that the WDT can expire before the WDTRSTO pin is continually asserted until the next time hardware reset is applied This reg ister is unaffected by WDT generated reset This register can only be...

Page 942: ...ated reset is asserted Table A 73 WDTTRIP Register Bit Descriptions RW Bit Name Description 3 0 TRIPVAL Current Value of Trip Counter This is the trip counter value programmable from 0 to 15 The numb...

Page 943: ...e WDT configuration space against accidental writes from the processor core Before attempting to write to the WDT configuration space the core must unlock the WDT by writing the command value 0xAD21AD...

Page 944: ...ecision clock generators is used in external source mode the SRU_CLK3 register pins 0 4 and or pins 5 9 specify the source SPORTs 6 and 7 receive their clocks from other routed sources but cannot rout...

Page 945: ...ample Rate Converter 0 Clock Input Input Sample Rate Converter 0 Clock Output Input Sample Rate Converter 1 Clock Input Input 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12...

Page 946: ...hannel 7 Clock Input Input Data Port Channel 5 Clock Input 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 SPDIF_EXTPLLCLK_I 14 10 External 512 x FS PLL Clock Inp...

Page 947: ...uffer 8 01000 0x8 DAI_PB09_O Pin Buffer 9 01001 0x9 DAI_PB10_O Pin Buffer 10 01010 0xA DAI_PB11_O Pin Buffer 11 01011 0xB DAI_PB12_O Pin Buffer 12 01100 0xC DAI_PB13_O Pin Buffer 13 PCG_SYNC_CLKC_I Pr...

Page 948: ...101 0x15 SPORT1_CLK_O SPORT 1 Clock 10110 0x16 SPORT2_CLK_O SPORT 2 Clock 10111 0x17 SPORT3_CLK_O SPORT 3 Clock 11000 0x18 SPORT4_CLK_O SPORT 4 Clock 11001 0x19 SPORT5_CLK_O SPORT 5 Clock 11010 0x1A D...

Page 949: ...Serial Port 1 Data Channel A Input SPORT1_DA_I 17 12 con t Serial Port 1 Data Channel B Input SPORT1_DB_I 23 18 Serial Port 0 Data Channel B Input SPORT0_DB_I 11 6 Serial Port 0 Data Channel A Input...

Page 950: ...23 18 SRC0_DAT_IP_I 17 12 con t Sample Rate Converter 0 Data Input Input 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 Sample Rate Converter 3 TDM Output Input...

Page 951: ...nput IDP1_DAT_I 17 12 Input Data Port 1 Data Input IDP1_DAT_I 17 12 con t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 Input Data Port 4 Data Input IDP4_DAT_I...

Page 952: ...07_O Pin Buffer 7 000111 0x7 DAI_PB08_O Pin Buffer 8 001000 0x8 DAI_PB09_O Pin Buffer 9 001001 0x9 DAI_PB10_O Pin Buffer 10 001010 0xA DAI_PB11_O Pin Buffer 11 001011 0xB DAI_PB12_O Pin Buffer 12 0011...

Page 953: ...T3_DA_O SPORT 3A Data 011011 0x1B SPORT3_DB_O SPORT 3B Data 011100 0x1C SPORT4_DA_O SPORT 4A Data 011101 0x1D SPORT4_DB_O SPORT 4B Data 011110 0x1E SPORT5_DA_O SPORT 5A Data 011111 0x1F SPORT5_DB_O SP...

Page 954: ...SPORTs 6 and 7 receive their frame syncs from other routed sources but cannot route their own frame syncs to other SPORTs or other peripherals internally through SRU If externally needed they have to...

Page 955: ...5 SPORT3_FS_I 19 15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 SRC2_FS_OP_I 29 25 SRC1_FS_OP_I 19 15 con t SRC2_FS_IP_I 24 20 SRC1_FS_OP_I 19 15 SRC0_FS_IP_I...

Page 956: ...le Rate Converter 3 Frame Sync Output Input SPDIF 3 Oversampling Clock Input 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 Input Data Port Channel 7 Frame Sync...

Page 957: ...uffer 9 01001 0x9 DAI_PB10_O Pin Buffer 10 01010 0xA DAI_PB11_O Pin Buffer 11 01011 0xB DAI_PB12_O Pin Buffer 12 01100 0xC DAI_PB13_O Pin Buffer 13 01101 0xD DAI_PB14_O Pin Buffer 14 01110 0xE DAI_PB1...

Page 958: ...ys 11010 0x1A DIR_FS_O SPDIF RX Frame Sync Output 11011 0x1B Reserved 11100 0x1C PCG_FSA_O Precision Frame Sync A Output 11101 0x1D PCG_FSB_O Precision Frame Sync B Output 11110 0x1E LOW Logic Level L...

Page 959: ...6 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 DAI_PB12_I 27 21 DAI_PB11_I 20 14 con t DAI_PB10_I 13 7 DAI_PB09_I 6 0 DAI_PB11_I 20 14 DAI Pin Buffer 11 Input DAI Pin Buffer 9 Input DAI Pin Buffer 10 Input D...

Page 960: ...x2 DAI_PB03_O Pin Buffer 3 0000011 0x3 DAI_PB04_O Pin Buffer 4 0000100 0x4 DAI_PB05_O Pin Buffer 5 0000101 0x5 DAI_PB06_O Pin Buffer 6 0000110 0x6 DAI_PB07_O Pin Buffer 7 0000111 0x7 DAI_PB08_O Pin Bu...

Page 961: ..._DA_O SPORT 2A Data 0011001 0x19 SPORT2_DB_O SPORT 2B Data 0011010 0x1A SPORT3_DA_O SPORT 3A Data 0011011 0x1B SPORT3_DB_O SPORT 3B Data 0011100 0x1C SPORT4_DA_O SPORT 4A Data 0011101 0x1D SPORT4_DB_O...

Page 962: ...tput 0110100 0x34 SPORT6_CLK_O SPORT 6 Clock 0110101 0x35 SPORT7_CLK_O SPORT 7 Clock 0110110 0x36 SPORT6_FS_O SPORT 6 Frame Sync 0110111 0x37 SPORT7_FS_O SPORT 7 Frame Sync 0111000 0x38 PCG_CLKA_O Pre...

Page 963: ...t 1001011 0x4B SPORT5_TDV_O SPORT5 Transmit Data Valid Output 1001100 0x4C SPORT6_TDV_O SPORT6 Transmit Data Valid Output 1001101 0x4D SPORT7_TDV_O SPORT7 Transmit Data Valid Output 1001110 0x4E DIR_L...

Page 964: ...nit D are used as input signals The miscellaneous signal routing registers correspond to the group E mis cellaneous signals listed in Table A 79 Figure A 75 SRU_EXT_MISCA Register RW INV_MISCA5_I Inve...

Page 965: ...DAI_PB07_O Pin Buffer 7 Output 00111 0x7 DAI_PB08_O Pin Buffer 8 Output 01000 0x8 DAI_PB09_O Pin Buffer 9 Output 01001 0x9 DAI_PB10_O Pin Buffer 10 Output 01010 0xA DAI_PB11_O Pin Buffer 11 Output 01...

Page 966: ...c 10110 0x16 SPORT2_FS_O SPORT2 Frame Sync 10111 0x17 SPORT3_FS_O SPORT3 Frame Sync 11000 0x18 SPORT4_FS_O SPORT4 Frame Sync 11001 0x19 SPORT5_FS_O SPORT5 Frame Sync 11010 0x1A DIT_BLKSTART_O S PDIF T...

Page 967: ...t 3 Pin Buffer Enable Input PBEN03_I DAI Port 1 Pin Buffer Enable Input PBEN01_I DAI Port 4 Pin Buffer Enable Input PBEN04_I DAI Port 2 Pin Buffer Enable Input PBEN02_I PBEN03_I 23 18 con t 31 30 29 2...

Page 968: ...ble Input PBEN14_I DAI Port 12 Pin Buffer Enable Input PBEN12_I PBEN13_I 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 DAI Port 20 Pin Buffer Enable Input PBEN2...

Page 969: ...1 0xB SPORT0_DB_PBEN_O SPORT 0 Data Channel B Output Enable 001100 0xC SPORT1_CLK_PBEN_O SPORT 1 Clock Output Enable 001101 0xD SPORT1_FS_PBEN_O SPORT 1 Frame Sync Output Enable 001110 0xE SPORT1_DA_P...

Page 970: ...24 SPORT7_CLK_PBEN_O SPORT 7 Clock Output Enable 100101 0x25 SPORT7_FS_PBEN_O SPORT 7 Frame Sync Output Enable 100110 0x26 SPORT7_DA_PBEN_O SPORT 7 Data Channel A Output Enable 100111 0x27 SPORT7_DB_P...

Page 971: ..._SCLK_I SR_LAT or DAI pin buffers 1 8 Figure A 81 and Table A 81 show the list of sources and programmable options for SR_SCLK_I and SR_LAT_I input signals Figure A 81 SR_CLK_SHREG Register RW Table A...

Page 972: ...rt 7 Frame Sync Output 10010 0x12 SR_SCLK External SR_CLK Pin 10011 0x13 SR_LAT External SR_LAT Pin 10100 0x14 PCG_CLKA_O PCG Clock A Output 10101 0x15 PCG_CLKB_O PCG Clock B Output 10110 0x16 PCG_FSA...

Page 973: ...Leve Low 0 00001 0x1 HIGH Logic Level High 1 00010 0x2 SPORT0_DA_O Sport 0 Data Channel A 00011 0x3 SPORT0_DB_O Sport 0 Data Channel B 00100 0x4 SPORT1_DA_O Sport 1 Data Channel A 00101 0x5 SPORT1_DB...

Page 974: ...ate 01111 0xF SPORT6_DB_O Sport 6 Data Channel B 10000 0x10 SPORT7_DA_O Sport 7 Data Channel A 10001 0x11 SPORT7_DB_O Sport 7 Data Channel B 10010 0x12 SR_SDI External SR_SDI Pin 10011 0x13 DAI_P01_O...

Page 975: ...C DAI_IRPTL_HS RO High priority interrupt latch register Shadow high priority interrupt latch register DAI_IRPTL_L ROC DAI_IRPTL_LS RO Low priority interrupt latch register Shadow low priority interru...

Page 976: ...port SPORT registers Figure A 84 DAI_IRPTL_x Register IDP_DMA3_INT IDP_DMA2_INT IDP_DMA1_INT IDP_DMA0_INT IDP_FIFO_GTN_INT DIR_VALID_INT DIR_LOCK_INT DIR_CRCERROR_INT DIR_NOSTREAM_INT DIR_ERROR_INT D...

Page 977: ...orts SPORT 0 through 7 These registers change depending on operating mode Figures and bit descriptions are provided as follows Serial mode Figure A 86 and Table A 84 on page A 153 I2 S and Left Justif...

Page 978: ...Buffer Hang Disable LAFS Late Frame Sync SCHEN_A DMA Channel A Chaining Enable SDEN_B DMA Channel B Enable SCHEN_B DMA Channel B Chaining Enable FS_BOTH Frame Sync Both SPEN_A DIFS Data Independent F...

Page 979: ...using law 11 Compand using A law Serial Data Channel B Type Formatting For Standard serial mode B channels companding mode is unavailable 0 Right justify zero fill unused MSBs 1 Right justify sign ext...

Page 980: ...rds and stored in NW word space in internal memory the 16 bit words can be read or written with SW space addresses 0 Disable 16 to 32 bit word packing 1 Enable 16 to 32 bit word packing 10 ICLK Intern...

Page 981: ...cleared 0 14 IFS Internal Frame Sync Select Selects whether the serial port uses an internally generated frame sync if set 1 or uses an external frame sync if cleared 0 15 DIFS Data Independent Frame...

Page 982: ...data is present in both transmit buffers TXSPxA and TXSPxB If cleared 0 a frame sync is issued if data is present in either transmit buffers When a SPORT is configured as a receiver if FS_BOTH is set...

Page 983: ...transmit data whenever they detect a SPORTx_FS signal 0 No SPORTx_FS signal occurred while TXSPxA B buffer is empty 1 SPORTx_FS signal occurred while TXSPxA B buffer is empty If FSR 0 DERR_x is set wh...

Page 984: ...Channel First Select DERR_A Channel A Error Status SDEN_A DMA Channel A Enable DXS_B 28 27 Data Buffer Channel B Status DERR_B Channel B Error Status SPTRAN SPORT Transaction SPEN_B SPORT Enable B BH...

Page 985: ...PMODE Sport Operation Mode 1 Selects the I2 S or left justified mode Bit 17 is used to select either of both modes 14 12 Reserved 15 DIFS Data Independent Frame Sync Select 0 Serial port uses a data d...

Page 986: ...fer or read an empty receive buffer FIFO 1 Ignore a core hang 24 SPEN_B Enable Channel B Serial Port 0 Serial port A channel disabled 1 Serial port A channel enabled 25 SPTRAN Data Direction Control T...

Page 987: ...ndicates whether the SPORTx_FS sig nal from an internal or external source occurred while the DXS_x buffer was full The SPORTs receive data whenever they detect a SPORTx_FS signal As a receiver it ind...

Page 988: ...Buffer Channel B Status DERR_B BHD Buffer Hang Disable SCHEN_A SPORT DMA Channel A Chaining Enable SDEN_B SPORT DMA Channel B Enable SCHEN_B SPORT DMA Channel B Chaining Enable Channel B Error Status...

Page 989: ...ilable Serial Data Channel B Type Formatting 0 Right justify zero fill unused MSBs 1 Right justify sign extend unused MSBs The transmit buffer does not zero fill or sign extend transmit data words thi...

Page 990: ...is high 1 the SPORTs detects an active edge of an external frame sync and starts transmitting receiving only after that even if you enable SPORTs at any instant of active frame sync This is done only...

Page 991: ...ection Control This bit controls the data direction of the serial port channel A and B signals When cleared 0 the SPORT is configured to receive on both chan nels A and B When configured to receive th...

Page 992: ...ource occurred while the DXS_x buffer was full The SPORTs receive data whenever they detect a SPORTx_FS signal As a receiver it indicates when the channel has received new data while the receive buffe...

Page 993: ...ar to previous SHARCs 1 ETDINTEN External Transfer Done Interrupt If set interrupt occurs only after the last bit of last word in the DMA is shifter out If cleared inter rupt occurs when the DMA count...

Page 994: ...4 SCLK during the trans mission of last word in a DMA then the TX underflow error bit is set DERR_x bit even though this premature frame sync does not cause any underflow and the SPORT does not try to...

Page 995: ...SPMCTLx regis ter bit definitions the same value can be written into both SPMCTLx registers in order to make legacy programs for the ADSP 2136x processors operate correctly Figure A 90 SPMCTLx Registe...

Page 996: ...it 11 5 NCH Number of Multichannel Slots minus one Select the number of channel slots maximum of 128 to use for multichannel operation Valid values for actual number of channel slots range from 1 to 1...

Page 997: ...l 15 13 Reserved 22 16 RO CHNL Current Channel Selected Identify the currently selected transmit channel slot 0 to 127 23 MCEB Multichannel B Mode Enable Packed and multichannel B modes only One of tw...

Page 998: ...nding from the serial port s DTYPE selection to the word transmitted or received in that channel s position of the data stream When a channel s bit in these registers is cleared 0 the SPORT does not c...

Page 999: ...Detection 0 Disable 1 Enable 2 FSERR_EN Enable Frame Sync Error Detection 0 Disable 1 Enable 3 Reserved 4 W1C DERRA_STAT Channel A Interrupt Status SPTRAN 0 Receive overflow status SPTRAN 1 Transmit u...

Page 1000: ...s of serial data and a single channel of up to a 20 bit wide parallel data Input Data Port DMA Control Registers For information on these registers see Standard DMA Parameter Regis ters on page 2 4 Fi...

Page 1001: ...DE4 22 20 IDP_SMODE5 25 23 IDP_SMODE2 16 14 IDP_SMODE1 13 11 IDP_EN IDP_NSET 3 0 IDP_BHD IDP_DMA_EN IDP_CLROVER Channel 7 Serial Mode Select Channel 6 Serial Mode Select Channel 3 Serial Mode Select C...

Page 1002: ...ntinues until the FIFO has valid data in the case of reads or the FIFO has at least one empty location in the case of writes This can be used in debug operations 0 Core hang is enabled 1 Core hang is...

Page 1003: ...110 Right justified 18 bits 111 Right justified 16 bits Note the SMODEx bits define the IDP buffer input format for core access For I2S and left justified single channel modes it receives 32 bits of...

Page 1004: ...x must be set with IDP_DMA_EN bit for DMA transfer of data from channel x If the global DMA_EN bit is not set then this bit has no effect 0x00 all channels cleared 0xFF all channels enabled default 23...

Page 1005: ...plexing on page 23 28 Figure A 95 IDP_CTL2 Register Table A 92 IDP_CTL2 Register Bit Descriptions RW Bit Name Description 7 0 FAEx First Active Edge for Channel x 1 nth IDP channel starts shifting in...

Page 1006: ...t This bit selects which peripheral is connected to the PDAP unit 0 Data control bits are read from DAI pins 1 Data control bits are read from AMI_ADDR pins IDP_P12_PDAPMASK IDP_P16_PDAPMASK IDP_PDAP_...

Page 1007: ...signal Clearing this bit 0 causes data to latch on the rising edge default Notice that in all four packing modes described data is read on a clock edge but the specific edge used rising or falling is...

Page 1008: ...of ping pong DMA in each respective channel channel 7 0 0 DMA is not active 1 DMA is active IDP_FIFOSZ Number of Valid Data in IDP FIFO IDP_DMA7_STAT IDP_DMA6_STAT IDP_DMA3_STAT IDP_DMA4_STAT IDP_DMA...

Page 1009: ...all eight DMA channels These bits are set once IDP_DMA_EN is set and remain set until the last data of that channel is transferred Even if IDP_DMA_EN is set 1 this bit goes low once the required numbe...

Page 1010: ...s filters and data formats used in the sample rate converter For n 0 the register controls the SRC0 and SRC1 modules and for n 1 it controls the SRC2 and SRC3 modules x 0 2 and y 1 3 The bit settings...

Page 1011: ...able SRCy_SOFTMUTE SRCy_HARD_MUTE SRCy Hard Mute Enable SRCy_AUTO_MUTE SRCy Auto Hard Mute Enable from SPDIF RX SRCy_BYPASS SRCy De emphasis Filter SRCy Bypass Mode SRCy_DEEMPHASIS 23 22 SRCy_SMODEIN...

Page 1012: ...input sample rate SRCx_FS_IP_I signal as follows enables de emphasis on incoming audio data for SRC 0 2 00 No de emphasis 01 32 kHz 10 44 1 kHz 11 48 kHz 8 SRCx_SOFTMUTE Soft Mute Enables soft mute on...

Page 1013: ...UTEOUT bit in SRCRATx register Writes to the SRCCTLx register should be at least one cycle before setting the SRCx_ENABLE When setting and clearing this bit it should be held low for a minimum of 5 PC...

Page 1014: ...ength less than 24 bits is selected 0 Dithering is disabled default 1 Dithering is enabled 26 27 SRCy_SMODEOUT Serial Output Format Selects the serial output format for SRC 1 3 as follows 00 Left just...

Page 1015: ...Y SRC2 and SRC3 The registers are shown in Figure A 99 and Figure A 100 and described in Table A 97 30 Reserved 31 SRCy_ENABLE SRC Enable Enables SRC 1 3 When set 1 or when the sample rate frame sync...

Page 1016: ...tput Enabled SRC1 Ratio Bit Field SRC0 Ratio Bit Field SRC1 Mute Output Enabled 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRC3_RATIO 30 16 SRC3_MUTEOUT SRC2...

Page 1017: ...pling Ratio of Frame Syncs These bits can be read to find the ratio of output to input sampling frequency SRCx_FS_OP_I SRCx_FS_IP_I This ratio is reported in 4 11 integer fraction format where the 15...

Page 1018: ...FSxPHASE_HI Phase for Frame Sync A B C D This field represents the upper half of the 20 bit value for the channel A B C D frame sync phase See also FSXPHASE_LO Bits 29 20 in Table A 99 30 ENFSx Enable...

Page 1019: ...r half of the 20 bit value for the channel A B C D frame sync phase See also FSXPHASE_HI Bits 29 20 in PCG_CTLx1 described on on page A 192 30 FSxSOURCE Frame Sync Source Master clock source for frame...

Page 1020: ...appear for example A B C D any clock unit can be chosen If the STROBEA B C D bits of the pulse width control register PCG_PW PCG_PW2 is reset to 0 then the input is directly passed to the frame sync o...

Page 1021: ...Mode RW Bit Name Description 0 STROBEx One Shot Frame Sync A C Frame sync is a pulse with dura tion equal to one period of the MISCA2_I signal PCG A MISCA4_I signal PCG C repeating at the beginning of...

Page 1022: ...ve low frame sync 31 18 Reserved In bypass mode bits 31 18 are ignored Figure A 105 PCG_SYNC1 Register Table A 101 PCG_PWx Register Bit Descriptions in Bypass Mode RW Cont d Bit Name Description Enabl...

Page 1023: ...CLKASOURCE bit 1 PCLK selected for clock A 3 FSA_SOURCE_IOP Enable Frame Sync A Input Source 0 Output selected by FSASOURCE bit 1 PCLK selected for frame sync A 16 FSB_SYNC Enable Synchronization of F...

Page 1024: ...Frame Sync C Input Source 0 Output selected by FSCSOURCE bit 1 PCLK selected for frame sync C 16 FSD_SYNC Enable Synchronization of Frame Sync D With External Frame Sync 0 Frame sync disabled 1 Frame...

Page 1025: ...mit Control Register DITCTL This 32 bit register s bits are shown in Figure A 107 and described in Table A 104 17 CLKD_SYNC Enable Synchronization of Clock D With External Frame Sync 0 Clock disabled...

Page 1026: ...ncy Mode Enable 0 2 channel mode 1 SCDF mode 5 DIT_SCDF_LR Select Single Channel Double Frequency Mode 0 Left channel 1 Right channel DIT_EN DIT_MUTE DIT_VALIDL DIT_VALIDR DIT_B0CHANR 31 24 Channel St...

Page 1027: ...0 Manually start block transfer according to input stream status bits 1 Automatically start block transfer 10 DIT_VALIDL Validity Bit A Use with channel status buffer 11 DIT_VALIDR Validity Bit B Use...

Page 1028: ...nnel and six user bits buffer registers associated with subframe B right channel Since a block owns 2 x 192 frames 24 bytes per frame are required for storage Note that status byte 0 is available in t...

Page 1029: ...ted with subframe A left channel and six user bits buffer registers associated with subframe B right channel These registers are listed with their locations in Table A 107 and Table A 108 DITCHANB2 BY...

Page 1030: ...ver Registers The following sections describe the receiver registers Receive Control Register DIRCTL This 32 bit register described in Table A 109 is used to set up error con trol and single channel d...

Page 1031: ...sample 10 Send zeros after the last valid sample 11 Soft mute of the last valid audio is performed as if NOS TREAM is asserted This is valid only when linear PCM audio data is in the stream When non...

Page 1032: ...clock input for S PDIF receiver 0 Use derived clock from the digital PLL 1 Use clock input from external PLL 8 Reserved 9 DIR_RESET Reset S PDIF Receiver By default the S PDIF receiver is always enab...

Page 1033: ...337M 0 Not non audio frame mode 1 Non audio frame mode 3 ROC DIR_VALID Validity Bit ORed bits of channel 1 and 2 0 Linear PCM data 1 Non linear audio data DIR_NOAUDIOL DIR_BIPHASEERROR Biphase Error...

Page 1034: ...crementing it to zero over a period of 4096 frames During this time the PLL three states the charge pump until the soft mute has been completed If non linear PCM audio data is in the AES3 SPDIF stream...

Page 1035: ...eceiver stores a maximum of 5 bytes 40 bit status informa tion Note that status byte 0 is available in the DIRCTL register This 32 bit register is described in Table A 112 Real Time Clock Registers Th...

Page 1036: ...bled 1 Seconds interrupt enabled 2 MIN_INTEN Minutes Interrupt Enable 0 Minutes interrupt disabled 1 Minutes interrupt enabled 3 HR_INTEN Hours Interrupt Enable 0 Hours interrupt disabled 1 Hours inte...

Page 1037: ...Enable 0 Days interrupt disabled 1 Days interrupt enabled 5 ALRM_INTEN Alarm Interrupt Enable 0 Alarm interrupt disabled 1 Alarm interrupt enabled 6 DAYALRM_INTEN Day Alarm Interrupt Enable 0 Day ala...

Page 1038: ...o RTC_CLOCK RTC_ALARM RTC_SWTCH or RTC_INIT is over 2 SEC Second Event Flag 0 Second event has not occurred 1 Second event has occurred 3 MIN Minute Event Flag 0 Minute event has not occurred 1 Minute...

Page 1039: ...nerated in this case The register can be programmed to any value between 0 and 216 1 seconds that is a range of 18 hours 12 minutes and 15 seconds 5 DAY Day Event Flag 0 Day event has not occurred 1 D...

Page 1040: ...id time values are forbidden Alarm Register RTC_ALARM This register shown in Figure A 114 is programmed by software for the time in hours minutes and seconds the alarm interrupt occurs Reads and write...

Page 1041: ...des the calibration function powers down the unit and grounds these buses Figure A 114 RTC Alarm Register RW Figure A 115 RTC_INIT Register 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 31 30 29 28 27 26 25 2...

Page 1042: ...n RTC oscillator 0 to power up RTC oscillator This bit must be compulsorily written once during first RTC oscillator power up 0 RTC oscillator runnng 1 Powers down RTC oscillator 5 RTC_READEN Output B...

Page 1043: ...ed on reading RTC_INITSTAT 1 DAYALRM_PEND RTC Power Down Indicates that an alarm has occurred Useful if core has powered down or reset in the middle 0 No day alarm has occurred 1 A day alarm had occur...

Page 1044: ...d should be set to logic low The registers and input signals for group A are summarized in Figure A 118 through Figure A 123 and Table A 118 Table A 117 SR_CTL Register Bit Descriptions RW Bit Name De...

Page 1045: ...lect Input SPI_MISO_I 9 5 SPI MISO Input SPI_MOSI_I 4 0 SPI MOSI Input SPI_CLK_I 19 15 SPI Clock Input 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 TWI_CLK_I 2...

Page 1046: ...5 Timer 1 Input TIMER0_I 4 0 Timer 0 Input FLAG4_I 14 10 Flag 4 Input 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 FLAG12_I 29 25 Flag 12 Input FLAG10_I 19 15...

Page 1047: ...Flag 15 Input FLAG14_I 9 5 Flag 14 Input FLAG13_I 4 0 Flag 13 Input 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7 5 6 4 2 1 14 12 11 10 13 15 MISCB0_I 19 15 MISCB0_I 19 15 Miscellaneous B...

Page 1048: ...1010 0xA DPI_PB09_O External Pin 9 01011 0xB DPI_PB10_O External Pin 10 01100 0xC DPI_PB11_O External Pin 11 01101 0xD DPI_PB12_O External Pin 12 01110 0xE DPI_PB13_O External Pin 13 01111 0xF DPI_PB1...

Page 1049: ...I 29 24 DPI pin buffer 5 Input DPI_PB03_I 17 12 con t DPI Pin Buffer 3 Input DPI_PB04_I 23 18 DPI Pin Buffer 4 Input DPI_PB03_I 17 12 DPI_PB02_I 11 6 DPI Pin Buffer2 Input DPI_PB01_I 5 0 DPI Pin Buffe...

Page 1050: ...11 0x7 DPI_PB06_O External Pin 6 001000 0x8 DPI_PB07_O External Pin 7 001001 0x9 DPI_PB08_O External Pin 8 001010 0xA DPI_PB09_O External Pin 9 001011 0xB DPI_PB10_O External Pin 10 001100 0xC DPI_PB1...

Page 1051: ..._O Slave Select 3 from SPI 011100 0x1C SPIB_MISO_O MISO from SPIB 011101 0x1D SPIB_MOSI_O MOSI from SPIB 011110 0x1E SPIB_CLK_O Clock Output from SPIB 011111 0x1F SPIB_FLG0_O Slave Select 0 from SPIB...

Page 1052: ...fer for each of the 14 DPI pins When the pins are not enabled driven they can be used as inputs The registers that control group C settings are shown in Figure A 127 through Figure A 129 101010 0x2A F...

Page 1053: ...I_PBEN03_I 17 12 DPI_PBEN02_I 11 6 DPI Pin Buffer Enable 2 Input DPI_PBEN01_I 5 0 DPI Pin Buffer Enable 1 Input DPI Pin Buffer Enable 3 Input 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 9 8 3 7...

Page 1054: ...UART 0 Transmitter 001001 0x9 Reserved 001010 0xA SPIMISO_PBEN_O Pin Enable for MISO from SPI 001011 0xB SPIMOSI_PBEN_O Pin Enable for MOSI from SPI 001100 0xC SPICLK_PBEN_O Pin Enable for CLK from SP...

Page 1055: ...Pin Enable for Flag 6 Output 011011 0x1B FLAG7_PBEN_O Pin Enable for Flag 7 Output 011100 0x1C FLAG8_PBEN_O Pin Enable for Flag 8 Output 011101 0x1D FLAG9_PBEN_O Pin Enable for Flag 9 Output 011110 0x...

Page 1056: ...peripheral interface DPI also has an interrupt controller similar to that in the DAI All of these interrupts are combined into a sin gle interrupt namely DPI_INT The DPI_IMASK register contains the s...

Page 1057: ...de information on the peripherals that are explicitly routed through the digital peripheral interface Figure A 131 DPI Interrupt Latch Mask Register Table A 121 DPI Interrupt Registers Register Descri...

Page 1058: ...ICTL SPICTLB Registers PACKEN TIMOD 0 1 Transfer Initiation Mode 8 Bit Packing Enable SPIEN SPI System Enable OPD Open Drain Output Enable for Data Pins SPIMS Master Slave Mode Bit CLKPL CPHASE MSBF M...

Page 1059: ...ate of this input pin is observable in bit 7 of the SPIFLGx register As master SPIDS can serve as an error detection input in a multimaster envi ronment The ISSEN bit enables this feature When ISSEN 1...

Page 1060: ...6 bits of the word written to the SPI buffer When receiving the SPI port packs the 16 bit word to the lower 32 bits of the RXSPI buffer while the upper bits in the register are zeros 32 bit word No pa...

Page 1061: ...be tied to GND See Pin Buffers as Open Drain on page 9 11 14 SPIEN SPI Port Enable Enables the SPI port If configured as a master SPIMS 1 and SPIEN 0 the MOSI and SPICLK outputs are disabled and the...

Page 1062: ...and then transmits 0xLM The receiver packs the two words received 0xJK and then 0xLM into a 32 bit word They appear in the RXSPI register as 0x00LM00JK if SGN is configured to 0 or L J 7 0xFFLMFFJK i...

Page 1063: ...e Read 0 SPI transmit read from internal memory 1 SPI receive write to internal memory SPICHS SPIDEN SPIDMAS DMA Transfer Status DMA Chain Loading Status SPIERRS DMA Error Status SPISx 13 12 DMA FIFO...

Page 1064: ...ng Enable 0 Disable 1 Enable 6 5 Reserved 7 WOC FIFOFLSH DMA FIFO Clear Clears the SPIS bit 0 Disable 1 Enable 8 INTERR Enable Interrupt on Error 0 Disable 1 Enable 9 RO SPIOVF Receive OverFlow Error...

Page 1065: ...or DPIMME bits are set 0 Successful DMA transfer 1 Errors during DMA transfer 15 RO SPIDMAS DMA Transfer Status 0 DMA idle 1 DMA in progress 16 RO SPICHS DMA Chain Loading Status 0 Chain idle 1 Chain...

Page 1066: ...ce when some other device tries to become the master In multimaster mode if the SPIDS input signal of a master is asserted low an error has occurred This means that another device is also trying to be...

Page 1067: ...bit 6 is set when a write to the TXSPI reg ister coincides with the load of the shift register The write to TXSPI can be via the software or the DMA This bit indicates that corrupt data may have been...

Page 1068: ...U2 be used for SPI slave select 0 Disable SPIFLGx output enable 1 Enable SPIFLGx output enable Note DS0EN bit is set in SPI master mode only 6 4 Reserved 7 RO ISSS Input Slave Service Select Reflects...

Page 1069: ...es Some UART registers share the same IOP address The UART0DLL registers are mapped to the same address as the UARTxTHR and UART0RBR registers The UART0DLH registers are mapped to the same address as...

Page 1070: ...1 and STP 0 1 Even parity when PEN 1 and STP 0 5 UARTSTP Stick Parity Forces parity to defined value if set and PEN 1 0 Parity transmitted and checked as 1 1 Parity transmitted and checked as 0 6 UART...

Page 1071: ...A 128 UART0LSR Register Bit Descriptions Bit Name Description 0 UARTDR Data Ready This bit is cleared when the UART receive buffer UARTxRBR is read 0 No new data 1 UARTx_RBR holds new data 1 ROC1 UART...

Page 1072: ...er register UART0RBR is read 0 No break interrupt 1 Break interrupt This indicates Rx pin was held low for more than the max word length 5 UARTTHRE UARTx_THR Empty The UARTTHRE bit indicates that the...

Page 1073: ...R bit in UART_LSR is set 1 UARTTBEIE Enable Transmit Buffer Empty Interrupt 0 No interrupt 1 Generate TX interrupt if THRE bit in UART_LSR is set 2 UARTLSIE Enable RX Status Interrupt 0 No interrupt 1...

Page 1074: ...t 3 1 ROC1 1 These bits are read only in the UARTxLRSH shadow register UARTISTAT In the Order of Interrupt Priority Highest First 011 Receive line status Read UART_LSR to clear interrupt request 100 A...

Page 1075: ...own in Figure A 140 Scratch Register UART0SCR This register Figure A 141 is used for general purpose data storage and does not control the UART hardware in any way Mode Register UART0MODE The UART mod...

Page 1076: ...n written with a 1 the next data byte goes to the lower byte position of the RBR register This is a write only bit and always returns zero on reads 2 UARTTX9 Enable 9 Bit Tx in Transmitter 0 I O mode...

Page 1077: ...T0_TX_O is three stated 11 UART0_TX_O is high Table A 132 UART0TXCTL Register Descriptions RW Bit Name Description 0 UARTEN Transmit Buffer Enable 0 Clear transmit buffer 1 Enables the transmit buffer...

Page 1078: ...eceive buffer this bit needs to be enabled regardless of core or DMA access 1 UARTDEN DMA Enable 0 Disables DMA 1 Enables DMA on the specified channel 2 UARTCHEN Chain Pointer DMA Enable 0 Disable cha...

Page 1079: ...timed events The internal time reference is derived from PCLK using the prescaled value PRESCALE fPCLK 10 MHz Table A 135 UART0RXSTAT Register Bit Descriptions RO Bit Name Description 0 UARTERRIRQ Rec...

Page 1080: ...nal time reference with a period of 10 MHz This is represented as a 7 bit binary value 7 TWIEN TWI Enable This bit must be set for slave or master mode operation It is recommended that this bit be set...

Page 1081: ...d during a valid transfer clock stretching ceases the serial data line is released and the current byte is not acknowledged 1 The slave is enabled Enabling slave and master modes of operation concurre...

Page 1082: ...ster mode operation does not affect the slave mode status bits 3 TWINAK Not Acknowledged 0 Slave receive transfer generates an ACK at the conclusion of a data transfer 1 Slave receive transfer generat...

Page 1083: ...it Descriptions RO Bit Name Description 0 TWISIDR Slave Transfer Direction This bit self clears if slave mode is disabled SEN 0 0 At the time of addressing the transfer direction was determined to be...

Page 1084: ...not effected 1 Master mode functionality is enabled A START condition is gen erated if the bus is idle 1 TWIMLEN Master Address Length 0 Address is 7 bit 1 Reserved Setting this bit to one causes unpr...

Page 1085: ...zero a STOP or restart condition is issued Setting DCNT to 0xFF disables the counter In this transfer mode data continues to be transferred until it is concluded by setting the STOP bit 14 TWISDAOVR...

Page 1086: ...1010000 which corresponds to 0x50 When sending out the address on the bus the TWI controller appends the read write bit as appropriate based on the state of the MDIR bit in the master mode control reg...

Page 1087: ...th another master 2 W1C TWIANAK Address Not Acknowledged 0 The current master transfer has not detected a NAK during addressing 1 The current master transfer was aborted due to the detection of a NAK...

Page 1088: ...data line 1 An active zero is currently being sensed on serial data line The source of the active driver is not known and can be internal or external 7 TWISCLSEN Serial Clock Sense For use when direct...

Page 1089: ...e Buffer Flush 0 Normal operation of the receive buffer and its status bits 1 Flush the contents of the receive buffer and update the status to indicate the buffer is empty This state is held until th...

Page 1090: ...h receive buffer interrupts are generated Interrupts may be generated with each byte received or after two bytes are received 0 An interrupt TWIRXINT is set when TWIRXS indicates one or two bytes in t...

Page 1091: ...nsmit shift register Simultaneous accesses are allowed 00 FIFO is empty Either a single or double byte peripheral write of the FIFO goes through immediately 01 FIFO contains one byte of data A single...

Page 1092: ...curred A restart or stop condition has occurred during the data receive phase of a transfer 3 TWISOVF Slave Overflow 0 No overflow detected 1 The slave transfer complete TWISCOMP was set at the time a...

Page 1093: ...is 0 this bit is set each time TWITXS is updated to either 01 or 00 If TWITXINT2 is 1 this bit is set each time TWITXS is updated to 00 7 TWIRXINT Receive FIFO Service 0 No errors detected 1 The rece...

Page 1094: ...Enable 0 The corresponding interrupt source is prevented from asserting the interrupt output 1 The corresponding interrupt source asserts the interrupt output 4 TWIMCOM Master Transfer Complete Inter...

Page 1095: ...write which simplifies timer enable disable and can be accomplished with fewer instructions Example Instead of ustat3 dm TMCTL Timer Control Register bit set ustat3 TIM1DIS disables timer 1 dm TMCTL...

Page 1096: ...5 TMxCTL Register Table A 146 TMxCTL Register Bit Descriptions RW Bit Name Description 1 0 TIMODE Timer Mode 00 Reset 01 PWM_OUT mode TIMODEPWM 10 WDTH_CAP mode TIMODEW 11 EXT_CLK mode TIMODEEXT 2 PUL...

Page 1097: ...TIMxEN bit is set or cleared For example writing a one to bit 8 sets the TIM0EN bit writing a one to bit 9 clears it Writing a one to both bit 8 and bit 9 clears TIM0EN Reading the status register re...

Page 1098: ...e 5 RO TIM1OVF Timer 1 Overflow Error Also an output 7 6 Reserved 8 TIM0EN Timer 0 Enable Enable timer 0 9 W1C TIM0DIS Timer 0 Disable Disable timer 0 10 TIM1EN Timer 1 Enable Enable timer 1 Table A 1...

Page 1099: ...CTL 0x1801 External Port Global Control 0xF0 AMICTL0 0x1804 AMI Control Register for Bank 1 0x0 AMICTL1 0x1805 AMI Control Register for Bank 2 0x0 AMICTL2 0x1806 AMI Control Register for Bank 3 0x0 AM...

Page 1100: ...rnal Port CH 1 DMA Internal Index Address 0x0 IMEP1 0x1834 External Port CH 1 DMA Internal Modifier 0x0 ICEP1 0x1835 External Port CH 1 DMA Internal Count 0x0 CPEP1 0x1836 External Port CH 1 DMA Chain...

Page 1101: ...0x1804 SDRAM Status 0x8 Global Serial Port Register SPERRSTAT 0x2300 Global SPORT Error Status 0x0 Serial Port Error Control Registers SPERRCTL0 0xC18 SPORT0 Error Control 0x0 SPERRCTL1 0xC19 SPORT1...

Page 1102: ...CS3 0xC0C SPORT 1 TDM RX Select CH127 96 0x0 MT0CCS0 0xC0D SPORT 0 TDM TX Compand Select CH31 0 0x0 MT0CCS1 0xC0E SPORT 0 TDM TX Compand Select CH63 32 0x0 MT0CCS2 0xC0F SPORT 0 TDM TX Compand Select...

Page 1103: ...SP0A 0xC60 SPORT 0A Transmit Data 0x0 RXSP0A 0xC61 SPORT 0A Receive Data 0x0 TXSP0B 0xC62 SPORT 0B Transmit Data 0x0 RXSP0B 0xC63 SPORT 0B Receive Data 0x0 TXSP1A 0xC64 SPORT 1A Transmit Data 0x0 RXSP...

Page 1104: ...and Select CH31 0 0x0 MR3CCS1 0x412 SPORT 3 TDM RX Compand Select CH63 32 0x0 MR3CCS2 0x413 SPORT 3 TDM RX Compand Select CH95 64 0x0 MR3CCS3 0x414 SPORT 3 TDM RX Compand Select CH127 96 0x0 SPMCTL3 0...

Page 1105: ...PORT 3B Transmit Data 0x0 RXSP3B 0x467 SPORT 3B Receive Data 0x0 Serial Port 4 and 5 Registers SPCTL4 0x800 SPORT 4 Control 0x0000 0000 SPCTL5 0x801 SPORT 5 Control 0x0000 0000 SPCTLN4 0x81A SPORT 4 C...

Page 1106: ...nternal Memory DMA Address 0x0 IMSP4A 0x841 Internal Memory DMA Access Modifier 0x0 CSP4A 0x842 Contains Number of DMA Transfers Remaining 0x0 CPSP4A 0x843 Points to Next DMA Parameters 0x0 IISP4B 0x8...

Page 1107: ...ster 2 0x0000 0000 DIV6 0x4802 SPORT 6 Divisor for TX RX SCLK6 and FS6 0x0 DIV7 0x4803 SPORT 7 Divisor for TX RX SCLK7 and FS7 0x0 SPMCTL6 0x4804 SPORT 6 TDM Control 0x0 MT6CS0 0x4805 SPORT 6 TDM TX S...

Page 1108: ...x0 IMSP6B 0x4845 Internal Memory DMA Access Modifier 0x0 CSP6B 0x4846 Contains Number of DMA Transfers Remaining 0x0 CPSP6B 0x4847 Points to Next DMA Parameters 0x0 IISP7A 0x4848 Internal Memory DMA A...

Page 1109: ...0x0 IMSPI 0x1081 Internal Memory DMA Access Modifier 0x0 CSPI 0x1082 Contains Number of DMA Transfers Remaining 0x0 CPSPI 0x1083 Points to Next DMA Parameters 0x0 SPIDMAC 0x1084 SPI DMA Control 0x0 SP...

Page 1110: ...C GP Timer 1 Width 0x0 SRU DAI Routing Registers SRU_CLK0 0x2430 SRU Clock Control 0 0x2526 30C2 SRU_CLK1 0x2431 SRU Clock Control 1 0x3DEF 7BDE SRU_CLK2 0x2432 SRU Clock Control 2 0x3DEF 7BDE SRU_CLK...

Page 1111: ...Control 0x3DEF 7BDE SRU_PBEN0 0x2478 SRU Pin Enable 0 0x0E24 82CA SRU_PBEN1 0x2479 SRU Pin Enable 1 0x1348 D30F SRU_PBEN2 0x247A SRU Pin Enable 2 0x1A55 45D6 SRU_PBEN3 0x247B SRU Pin Enable 3 0x1D71 F...

Page 1112: ...Latch 0x0 DAI_IRPTL_HS 0x248C Shadow DAI High Priority Interrupt Latch 0x0 DAI_IRPTL_LS 0x248D Shadow DTDMAI Low Priority Interrupt Latch 0x0 DPI Interrupt Registers DPI_IRPTL 0x1C32 DPI Interrupt Lat...

Page 1113: ...A 0x0 IDP_DMA_I3A 0x240B IDP DMA Channel 3 Index A for Ping Pong DMA 0x0 IDP_DMA_I4A 0x240C IDP DMA Channel 4 Index A for Ping Pong DMA 0x0 IDP_DMA_I5A 0x240D IDP DMA Channel 5 Index A for Ping Pong D...

Page 1114: ..._DMA_C4 0x2424 IDP DMA Channel 4 Count 0x0 IDP_DMA_C5 0x2425 IDP DMA Channel 5 Count 0x0 IDP_DMA_C6 0x2426 IDP DMA Channel 6 Count 0x0 IDP_DMA_C7 0x2427 IDP DMA Channel 7 Count 0x0 IDP_DMA_PC0 0x2428...

Page 1115: ...t Priority Control Registers PICR0 0x2200 Programmable Interrupt Priority Control 0 0x0A41 8820 PICR1 0x2201 Programmable Interrupt Priority Control 1 0x16A4 A0E6 PICR2 0x2202 Programmable Interrupt P...

Page 1116: ...1 0x0 PWMDBG1 0x301E PWM Debug Status 1 0x0 PWMPOL1 0x301F PWM Output Polarity Select 1 0x00FF PWMCTL2 0x3400 PWM Control 2 0x0 PWMSTAT2 0x3401 PWM Status 2 0x0009 PWMPERIOD2 0x3402 PWM Period 2 0x0...

Page 1117: ...emory DMA Control 0x0 IIMTMW 0x2C10 MTM DMA Destination Index 0x0 IIMTMR 0x2C11 MTM DMA Source Index 0x0 IMMTMW 0x2C0E MTM DMA Destination Modify 0x0 IMMTMR 0x2C0F MTM DMA Source Modify 0x0 CMTMW 0x2C...

Page 1118: ...FIRDMASTAT 0x5001 DMA Status Reg 0x0 FIRMACSTAT 0x5002 MAC Status 0x0 FIRDEBUGCTL 0x5004 Debug Control 0x0 FIRDBGADDR 0x5005 Debug Address 0x0 FIRDBGWRDATA 0x5006 Debug Data Write 0x0 FIRDBGRDDATA 0x...

Page 1119: ...a Write MS 8 Bits 0x0 IIRDBGRDDATA_L 0x5207 Debug Data Read LS 32 Bits 0x0 IIRDBGRDDATA_H 0x5208 Debug Data Read MS 8 Bits 0x0 IIRCTL2 0x5210 Channel Control 0x0 IIIIR 0x5211 Input Data Index 0x0 IMII...

Page 1120: ...0 DITCHANB4 0x24DD Transmit CH4 Subframe B 0x0 DITCHANB5 0x24DE Transmit CH5 Subframe B 0x0 S PDIF User Bit Status Registers DITUSRBITA0 0x24E0 Transmit User Bit CH0 Subframe A 0x0 DITUSRBITA1 0x24E1...

Page 1121: ...Output to Input Ratio 0x8000 8000 SRCRAT1 0x2499 SRC1 Output to Input Ratio 0x8000 8000 UART Registers UART0LCR 0x3C03 UART0 Line Control 0x0 UART0LSR 0x3C05 UART0 Line Status 0x60 UART0THR 0x3C00 UAR...

Page 1122: ...us 0x0 TWI Registers TWIDIV 0x4400 SCL Clock Divider 0x0 TWIMITR 0x4404 Master Internal Time Reference 0x0 TWISCTL 0x4408 Slave Mode Control 0x0 TWISSTAT 0x440C Slave Mode Status 0x0 TWISADDR 0x4410 S...

Page 1123: ...rt 0 Shadow Output RX Buffer 0x0 LSTAT0_ SHADOW 0x4C03 Link Port 0 Shadow Status 0x0 IILB0 0x4C18 Link Port 0 Internal Index 0x0 IMLB0 0x4C19 Link Port 0 Internal Modifier 0x0 CLB0 0x4C1A Link Port 0...

Page 1124: ...he IP Version 0x202 MLB_SBCR 0x4108 Synchronous Base Address 0x0 MLB_ABCR 0x4109 Asynchronous Base Address 0x0 MLB_CBCR 0x410A Control Base Address 0x0 MLB_IBCR 0x410B Isochronous Base Address 0x0 MLB...

Page 1125: ...4 Control 0x0 MLB_CSCR4 0x4121 Channel 4 Status 0x8000 0000 MLB_CCBCR4 0x4122 Channel 4 Current Buffer RX Buffer in I O Mode 0x0 MLB_CNBCR4 0x4123 Channel 4 Next Buffer TX Buffer in I O Mode 0x0 MLB_...

Page 1126: ...0x0 MLB_CNBCR9 0x4137 Channel 9 Next Buffer TX Buffer in I O Mode 0x0 MLB_LCBCR9 0x41A9 Channel 9 Local Channel Buffer Control 0x0040 0009 MLB_CECR10 0x4138 Channel 10 Control 0x0 MLB_CSCR10 0x4139 Ch...

Page 1127: ...ffer Control 0x0040 000E MLB_CECR15 0x414C Channel 15 Control 0x0 MLB_CSCR15 0x414D Channel 15 Status 0x8000 0000 MLB_CCBCR15 0x414E Channel 15 Current Buffer RX Buffer in I O Mode 0x0 MLB_CNBCR15 0x4...

Page 1128: ...LB_CCBCR20 0x4162 Channel 20 Current Buffer RX Buffer in I O Mode 0x0 MLB_CNBCR20 0x4163 Channel 20 Next Buffer TX Buffer in I O Mode 0x0 MLB_LCBCR20 0x41B4 Channel 20 Local Channel Buffer Control 0x0...

Page 1129: ...X Buffer in I O Mode 0x0 MLB_LCBCR25 0x41B9 Channel 25 Local Channel Buffer Control 0x0040 0019 MLB_CECR26 0x4178 Channel 26 Control 0x0 MLB_CSCR26 0x4179 Channel 26 Status 0x8000 0000 MLB_CCBCR26 0x4...

Page 1130: ...Next Buffer TX Buffer in I O Mode 0x0 MLB_LCBCR30 0x41BE Channel 30 Local Channel Buffer Control 0x0040 001E Shift Register Register SR_CTL 0x24F0 Shift Register Control 0x0 Watchdog Timer Registers W...

Page 1131: ...sor Hardware Reference A 305 Registers Reference RTC_INIT 0x4CA6 Real Time Clock Initialization 0x0 RTC_INITSTAT 0x4CA7 Real Time Clock Initialization Status 0x0 Register Mnemonic Address Description...

Page 1132: ...Register Listing A 306 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Page 1133: ...o clear the interrupt causes a certain amount of latency due to the existence of register write effect latency Interrupt driven data transfers core or DMA from any peripheral that generates interrupts...

Page 1134: ...r0 dm PWMGSTAT force dummy read to terminate write rti 2 Add sufficient NOP instructions after a write In the worst case programs need to add ten NOP instructions after a write as shown in the example...

Page 1135: ...ore exiting an interrupt routine For the W1C mechanism programs must write into the specific bit of the latch register in order to terminate the interrupt properly If the acknowledge mechanism rules a...

Page 1136: ...denotes default routing Table B 2 also defines the PICR bits which should be programmed to select the source for each priority interrupt Priority programming can be accomplished by changing the sourc...

Page 1137: ...C Processor Hardware Reference B 5 Peripheral Interrupt Control example if peripheral x should be given high priority the high priority priority interrupt source should be set as that peripheral x www...

Page 1138: ...errupt P5I 0x40 PICR0 29 25 0x05 SPORT5 interrupt P6I 0x44 PICR1 4 0 0x06 SPORT0 interrupt P7I 0x48 PICR1 9 5 0x07 SPORT2 interrupt P8I 0x4C PICR1 14 10 0x08 SPORT4 interrupt P9I1 0x50 PICR1 19 15 0x0...

Page 1139: ...xI 0x15 UART0 transmit interrupt TWII 0x17 Two wire interface interrupt PWMI 0x18 PWM interrupt LP0I RTCI 0x19 Link port 0 RTC interrupt LP1I 0x1A Link port 1 interrupt ACC0I 0x1B Accelerator 01 inter...

Page 1140: ...tat1 dm PICR2 bit set ustat1 P17I4 P17I3 PWMI 0x18 I4 0 11000 bit clr ustat1 P17I2 P17I1 P17I0 dm PICR2 ustat1 Figure B 1 PICR0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0...

Page 1141: ...1 P10I 24 20 Programmable Interrupt 10 P9I 19 15 Programmable Interrupt 9 Programmable interrupt 6 P6I 4 0 programmable interrupt 8 P8I 14 10 P9I 19 15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 1142: ...r Hardware Reference Figure B 4 PICR3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P18...

Page 1143: ...ls noted in Table C 1 Table C 1 Audio Format Availability Frame Format SPORTs IDP SIP ASRC Input ASRC Output S PDIF Tx S PDIF Rx PCG Serial Yes Yes I2 S Yes Yes Yes Yes Yes Yes Yes Left justified Yes...

Page 1144: ...nsmitted or received through their serial ports For convenience most AFE analog front end devices operate with 16 bit word lengths for both data and sta tus transfer between the AFE and processor The...

Page 1145: ...devices Today the I2 S protocol has become the stan dard method of communicating with consumer and professional audio products The I2 S protocol provides transmission of 2 channel stereo Pulse Code Mo...

Page 1146: ...has a bit clock frequency of 2 8224 MHz The word select clock lets the device know whether channel 1 or channel 2 is currently being sent since I2 S allows two channels to be sent on the same data lin...

Page 1147: ...sync the other on the low seg ment of the frame sync Prior to development of the I2 S standard many manufacturers used a variety of non standard stereo modes Some compa nies continue to use this mode...

Page 1148: ...or supervisory processor it may be impractical if not impossible to dedicate a separate SPORT interface to each AFE connection The solution is to devise a way to connect a series of serial devices to...

Page 1149: ...2 packed I2S waveforms are the same as the wave forms used in TDM mode except that the frame sync is toggled for every frame and therefore emulates I2S mode So it is a hybrid between TDM and I2S mode...

Page 1150: ...bus use a packed TDM4 data format Figure C 3 illustrates a word length of 16 bits for a timing diagram of the packed TDM4 mode This figure is shown with a negative BCLK polarity a negative LRCLK polar...

Page 1151: ...in total with 192 data words transmitted for the A stereo channel and 192 data words transmitted for the B stereo channel The difference between the AES EBU and S PDIF protocol is the channel status b...

Page 1152: ...o sample word is suitable for direct analog conversion User data bits may be used in any way desired by the program The channel status bit conveys information about the status of the channel Examples...

Page 1153: ...8 unit intervals1 in length Figure C 4 Since the time slots correspond with the data bits the frame is often described as being 64 bits in length A frame is uniquely composed of two subframes The firs...

Page 1154: ...word with the LSB in time slot 8 Time slots 4 to 7 may be used for other applications Under these circumstances the bits in time slots 4 to 7 are designated auxiliary sample bits If the source provide...

Page 1155: ...carries user specified infor mation that may be used in any way This bit is set if the corresponding bit given with the left right sample is set 3 Channel status bit time slot 30 The channel status fo...

Page 1156: ...y the two subframes can carry successive samples of the same channel of data but at a sample rate that is twice the frame rate This is called single channel double frequency SCDF For more information...

Page 1157: ...ble these patterns violate the bi phase mark code rules thereby avoiding the possibility of data imitating the preambles A set of three preambles shown in Table C 2 are used These preambles are transm...

Page 1158: ...e dc free and provide clock recovery They differ in at least two states from any valid bi phase sequence Table C 2 Preambles Preamble Preceding state 0 Preceding state 1 Description X 11100010 0001110...

Page 1159: ...el receive frame sync select LMFS bit 10 20 AD1855 stereo DAC use with SPI 15 10 address AMI 3 84 AMI address map 3 14 core to external memory 3 27 address continued decoding address bank 3 27 3 62 de...

Page 1160: ...DIF 13 7 13 15 non linear data S PDIF 13 16 restriction with SPORTs 10 10 transmission standards SPORTs C 3 audio formats C 1 to C 9 audio modes C 2 to C 9 autobaud detection 20 6 automotive products...

Page 1161: ...r 2 33 chained DMA 2 23 2 29 2 32 2 34 chained DMA enable SCHEN_A and SCHEN_B bit A 156 A 160 chained DMA sequences 2 11 chain pointer CPSPI registers SPI 15 32 chain pointer CPSPx registers SPORTs 2...

Page 1162: ...ter 3 21 NOP 3 24 precharge 3 21 3 22 read write 3 22 self refresh 3 44 3 79 compand data in place 10 3 companding compressing expanding 10 3 compute block FFT 6 5 conditioning input signals 23 33 con...

Page 1163: ...ation sample 9 42 system design 9 4 DAI_IRPTL_RE register as replacement to IMASK 9 39 DAI registers pin status DAI_PIN_STAT A 230 data buffer FIR 6 33 direction control SPTRAN bit A 157 A 160 A 165 t...

Page 1164: ...R 6 45 SPI 4 21 15 27 15 28 SPORT 10 53 tools use in 1 5 decimation FIR 6 38 destination address 2 22 DIFS data independent frame sync select bit A 155 A 159 digital applications interface See DAI dig...

Page 1165: ...rrupts 4 19 SPI slave mode 15 31 15 32 SPORT chain status bits DMACHSxy A 171 SPORT status bit DMASxy A 171 standard non chained 2 23 starting stopping 2 29 DMA continued switching from receive to tra...

Page 1166: ...nal bus SDRAM 3 44 3 80 SPORT error control register A 172 TWI master mode 21 21 21 23 TWI repeat start 21 24 TWI slave transfer 21 11 21 20 errors continued UART baud rate 20 5 UART sampling 20 11 ev...

Page 1167: ...optimization 3 43 3 78 DMA registers 2 28 A 60 to A 63 external code throughput 3 119 external index addressing 2 28 external port continued feature summary 4 2 instruction packing 3 90 program contro...

Page 1168: ...6 6 packed and unpacked date 6 8 packing bits FFT_CPACKIN FFT_CPACKOUT 6 14 processing state 6 7 programming 6 26 read state 6 7 registers 6 5 repeat FFT_RPT bit 6 7 FFT accelerator continued repeat...

Page 1169: ...s 7 4 SPORT pins 10 12 FLAGx pins 10 12 15 9 floating point 1 1 40 bit IIR 6 61 FIR data format 6 42 floating point continued FIR multiplier 6 31 format select bit IIR IIR_FORTYBIT A 89 IIR accelerato...

Page 1170: ...11 23 DMA control registers A 174 DMA count IDP_DMA_Cx register 11 20 11 21 IDP continued DMA index IDP_DMA_Ix register 11 20 11 21 DMA modify IDP_DMA_Mx register 11 20 11 21 FIFO IDP_FIFO register 11...

Page 1171: ...DMASTAT register 6 56 DMA transfers 6 62 IIR accelerator continued floating point operations 6 59 internal memory 6 60 MAC unit 6 59 operating modes 6 61 single step 6 65 throughput 6 67 transposed fo...

Page 1172: ...6 link ports 4 16 MAC status FIR 6 65 masking 2 45 masking and latching 4 20 peripheral timers 16 18 polling 2 45 priority 2 48 interrupts continued priority interrupt control registers PICR B 4 restr...

Page 1173: ...k LRRQ_MSK A 65 transmit request mask LTRQ_MSK A 64 Link port control LCTL register A 64 Link port receive request status LxRRQ bits A 66 link ports chained DMA 2 15 transmit status LTRQ bit A 66 Link...

Page 1174: ...g pong DMA 8 17 data structure 8 7 data transfer core 8 8 DMA transfers 8 11 features 8 3 frame synchronization 8 7 MLB continued Generic Synchronous Packet Format GSPF 8 7 interrupts 8 14 I O mode tr...

Page 1175: ...15 26 15 27 mode fault multimaster error SPI DMA status MME bit 15 26 15 27 modes audio C 2 to C 9 MOSIx pins 15 8 15 14 most significant byte first MSBF bit A 234 MPEG 2 format 13 17 MSBF most signif...

Page 1176: ...Ax registers 14 13 A 191 A 192 division ratios 14 18 enable clock ENCLKx bit A 191 A 192 PCG continued enable frame sync ENFSx bit A 191 A 192 frame sync A source FSASOURCE bit 14 13 A 193 frame sync...

Page 1177: ...priority registers B 4 PICR register 2 48 B 6 pin buffer example 9 7 ping pong DMA 2 23 2 24 ping pong DMA IDP 11 21 pins ACK enabling A 22 A 49 descriptions 22 18 23 2 external memory 3 48 FLAGx 10 1...

Page 1178: ...le 6 71 programming model 6 68 TWI controller 21 19 pulse clock in serial ports 10 11 pulse frame sync delay in serial ports 10 33 pulse frame sync formula 10 9 pulse width count and capture WDTH_CAP...

Page 1179: ...ock register RTC_CLOCK 18 3 clock requirements 18 3 counters 18 4 digital watch 18 5 digital watch features 18 1 disabling 18 3 RTC continued error 18 8 event flags 18 14 18 15 flags list 18 15 initia...

Page 1180: ...SDPM A 53 power up sequence start SDPSS A 54 RAS setting SDTRAS A 53 RDC setting SDTRCD A 55 refresh delay RDIV A 59 row address width SDRAW A 55 RP setting SDTRP A 53 self refresh enable SDSRF A 54...

Page 1181: ...inear audio data 13 16 output routing 13 8 pin descriptions receiver 13 4 pin descriptions transmitter 11 3 13 3 preambles C 16 programming guidelines 13 6 S PDIF continued serial clock input 13 6 ser...

Page 1182: ...15 33 block diagram 15 8 booting 23 12 23 15 boot packing 23 17 chained DMA 2 14 chaining DMA 15 13 15 21 15 23 15 25 15 32 SPI continued change clock polarity 15 29 changing configuration 15 29 cloc...

Page 1183: ...error SPIOVF 15 26 15 37 15 38 seamless transfer SMLS A 236 send zero SENDZ A 233 sign extend SGN A 236 SPI bits continued word length WL A 234 SPICHEN_A and SPICHEN_B SPI DMA chaining enable bits A 1...

Page 1184: ...AFS A 155 A 159 loopback mode SPL A 170 multichannel frame delay MFD A 170 multichannel mode enable MCEA A 170 number of channels NCH 10 35 SPORT bits continued number of multichannel slots NCH A 170...

Page 1185: ...10 26 framed vs unframed data example 10 28 frame sync and serial word length 10 10 SPORTs continued frame sync delay 10 33 full duplex operation 10 11 input output FLAGx pins 10 12 internal clock sel...

Page 1186: ...ng control SRU_FSx registers A 128 group A clock signals 9 24 A 218 SRU continued group E miscellaneous signals A 138 to A 140 inputs 9 16 outputs 9 16 register use of 9 20 serial ports and 10 5 signa...

Page 1187: ...esign baud rate init value 23 13 boot times kernel 23 22 bypass capacitors 23 36 clock distribution 23 33 conditioning input signals 23 33 crosstalk 23 37 decoupling capacitors 23 36 system design con...

Page 1188: ...TMxCTL timer control registers A 270 TMxPRD peripheral timer period registers 16 4 TMxSTAT timer global status and control register A 271 TMxW peripheral timer width registers 16 5 TMxW peripheral ti...

Page 1189: ...registers clock divider TWIDIV A 254 RXTWI16 16 bit receive FIFO register 21 14 RXTWI8 8 bit receive FIFO 21 13 TWIMADDR master mode address A 260 TWI controller registers continued TWIMCTL master mod...

Page 1190: ...4 A 249 interrupt enable register UARTxIER A 246 interrupt identification register UARTxIIR A 247 line control register UARTxLCR A 243 line status register UARTxLSR A 245 receive buffer register UARTx...

Page 1191: ...ng 19 8 WDTH_CAP width capture mode 16 2 16 12 19 2 window processing IIR 6 61 word length 10 10 word length SLEN bits 10 29 10 31 word packing enable packing 16 bit to 32 bit words A 154 A 159 A 163...

Page 1192: ...Index I 34 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...

Reviews:

No comments