Analog Devices SHARC ADSP-214 Series, Hardware Reference Manual, Page: 830 / 1192

System and Power Management Registers
A-4 ADSP-214xx SHARC Processor Hardware Reference
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Many registers have reserved bits. When writing to a register, pro-
grams may only clear (write zero to) the register’s reserved bits.
System and Power Management
Registers
The registers described in the following sections are used to control system
wide operations and power management.
System Control Register (SYSCTL)
The
SYSCTL
register configures memory use, interrupts, and many aspects
of pin multiplexing. ( For more information, see “Pin Multiplexing” on
page 23-28. ) Bit descriptions for this register are shown in Figure A-1 and
described in Table A-2 .
WO Write-Only WO bits are used primarily in control/status register
to trigger events like self-refresh or power-up
sequence for SDRAM. Note that these bit type
always read zero
WOC Write-Only-to-Clear WOC bits are used primarily in control/status regis-
ter to flush data FIFOs and to clear its status bits.
W1C Write-1-to-Clear W1C bits are sticky bits used primarily in status
registers during interrupt acknowledge for PWM
and timers. These bits are sticky and their status is
only cleared after a write.
Table A-1. Bit Type Usage (Cont’d)
Bit Type Description Usage
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