Analog Devices SHARC ADSP-214 Series, Hardware Reference Manual, Page: 144 / 1192

Asynchronous Memory Interface
3-14 ADSP-214xx SHARC Processor Hardware Reference
Parameter Timing
This section describes the programmable timing parameter for the AMI.
The AMI controller allows to program access timing parameters (wait
states for idle or hold cycles) with the effect being flexible and efficient
whether initiation is from the core or from DMA, and the sequence of
transactions (read followed by read, read followed by write, and so on).
Idle Cycles
An idle cycle is inserted by default for an AMI read followed by write or a
read followed by a read from a different bank or a read followed by an
external access by another device in order to provide bus contention.
If an idle cycle is programmed for a particular bank, then a minimum of 1
idle cycle is inserted for reads even if they are from the same bank. In
order to achieve better read throughput, an idle cycle should be
programmed as 0. For more information refer to the product specific data
sheet.
Address Mapping
The processors have the ability to use logical addressing when an external
memory smaller than 32 bits is used. When logical addresses are used,
multiple external addresses seen by the memory correspond to a single
internal address, depending on the width of the memory being accessed,
and the packing mode setting of the AMI controller.
The external physical address map is shown in Table 3-3 .
For an external bus width of 8 bits with packing enabled (
PKDIS
= 0), the
external physical address
ADDR23–0
generation is
ADDR23–2
= bits 21–0 in
the address being supplied to the external port by the core or DMA con-
troller. Here,
ADDR1–0
corresponds to the 1st/2nd/3rd/4th 8-bit word.
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