Analog Devices SHARC ADSP-214 Series, Hardware Reference Manual, Page: 1156 / 1192

AES/EBU/SPDIF Formats
C-14 ADSP-214xx SHARC Processor Hardware Reference
words, number of audio channels, sampling frequency, sample
address code, alphanumeric source and destination codes, and
emphasis.
Channel status information is organized in 192-bit blocks, subdi-
vided into 24 bytes. The first bit of each block is carried in the
frame with preamble Z.
4. Parity bit (time slot 31). The parity bit indicates that time slots 4
to 31 inclusive will carry an even number of ones and an even
number of zeros (even parity). The parity bit is automatically gen-
erated for each subframe and inserted into the encoded data.
The two subframes in a frame can be used to transmit two channels of
data (channel 1 in subframe 1, channel 2 in subframe 2) with a sample
rate equal to the frame rate. Alternatively, the two subframes can carry
successive samples of the same channel of data, but at a sample rate that is
twice the frame rate. This is called single-channel, double-frequency
(SCDF).
For more information, see “Data Output Mode” on page 13-12.
Channel Coding
To minimize the direct-current (dc) component on the transmission line,
to facilitate clock recovery from the data stream, and to make the interface
insensitive to the polarity of connections, time slots 4 to 31 are encoded in
bi-phase mark.
Each bit to be transmitted is represented by a symbol comprising two con-
secutive binary states. The first state of a symbol is always different from
the second state of the previous symbol. The second state of the symbol is
identical to the first if the bit to be transmitted is logic 0. However, it is
different if the bit is logic 1.
Figure C-6 shows that the ones in the original data end up with mid cell
transitions in the bi-phase mark encoded data, while zeros in the original
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