Analog Devices SHARC ADSP-214 Series, Hardware Reference Manual, Page: 197 / 1192

ADSP-214xx SHARC Processor Hardware Reference 3-67
External Port
The delay (in number of
DDR2_CLKx
cycles) desired between consecutive
refresh counter time-outs must be written to the
RDIV
field. A refresh
counter time-out triggers an auto-refresh command to the external DDR2
bank. Write the
RDIV
value to the
DDR2RRC
register before the DDR2
power-up sequence is triggered. Change this value only when the DDR2
controller is idle.
To calculate the value that should be written to the
DDR2RRC
register, use
the following equation:
RDIV
= (
DDR2_CLKx
×
t
REFI
) – (t
RAS
+ t
RP
) where:
• DDR2 Clock = DDR2 system clock frequency
• t
REFI
= DDR2 maximum average auto refresh period (in us). (Note
t
REFI
= t
REF
/Number of row addresses)
• t
RAS
= Active to precharge time (
DDR2_RAS
bit in the
DDR2CTL1
reg-
ister) in number of clock cycles
• t
RP
= RAS to precharge time (in the
DDR2CTL1
register) in number
of clock cycles
This equation calculates the number of clock cycles between the required
distributed refreshes, and subtracts the required delay between bank acti-
vate commands to the same bank (t
RC
= t
RAS
+ t
RP
). The t
RC
value is
subtracted, so that in the case where a refresh time-out occurs while a
DDR2 cycle is active, the refresh rate specification is guaranteed to be
met. The result from the equation should always be rounded down to an
integer.
Below is an example of the calculation of
RDIV
for a typical DDR2 mem-
ory in a system with a 200 MHz clock.
DDR2_CLKx
= 200 MHz
t
REFI
= 7.8
μ
s
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