Analog Devices SHARC ADSP-214 Series, Hardware Reference Manual, Page: 534 / 1192

Data Transfer
11-14 ADSP-214xx SHARC Processor Hardware Reference
Data Transfer
The data from each of the eight IDP channels is inserted into an eight reg-
ister deep FIFO, which can only be transferred to the core’s memory space
sequentially. Data is moved into the FIFO as soon as it is fully received.
One of two methods can be used to move data from the IDP FIFO to
internal memory:
• The core can remove data from the FIFO manually. This method
of moving data from the IDP FIFO is described in the next section,
“Core Transfers” on page 11-15 .
• Eight dedicated DMA channels can sort and transfer data. This
method of moving data from the IDP FIFO is described in “DMA
Transfers” on page 11-19 .
Data Buffer
The
IDP_FIFO
register provides information about the output of the
8-deep IDP FIFO which have been filled by the SIP or the PDAP units.
Normally, this register is used only to read and remove the top sample
from the FIFO. Channel encoding provides for eight serial input types
that correspond to the
IDP_SMODEx
bits in the IDP control registers. When
using channels 0–7 in serial mode, this register format applies. When
using channel 0 in parallel mode, refer to the description of the packing
bits for PDAP mode.

The information in Table 11-8 is not valid when data comes from
the PDAP channel.
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