a>b
a
b
Vpickup>
V
t
tReset1
t
t1
AND
TRST1
PU_ST1
OFF
Delay
ON
Delay
ANSI10000100-2-en.vsd
ANSI10000100 V2 EN
Figure 97:
Detailed logic diagram for step 1, definite time delay, DT operation
Pickup1
PICKUP
TRIP
tReset1
t1
ANSI10000037-2-en.vsd
ANSI10000037 V2 EN
Figure 98:
Example for step 1, Definite Time Delay stage 1 reset
1MRK 511 365-UUS A
Section 9
Voltage protection
Phasor measurement unit RES670 2.1 ANSI
293
Technical manual
Summary of Contents for Relion 670 Series RES670
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