Preliminary
Registers
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14.7.4.30 CM_TIMER6_CLKSEL Register
The CM_TIMER6_CLKSEL register selects the Mux select line for TIMER6 clock. It is shown and
described in the figure and table below
Figure 14-47. CM_TIMER6_CLKSEL Register
31
2
1
0
Reserved
CLKSEL
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-62. CM_TIMER6_CLKSEL Register Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1-0
CLKSEL
Selects the Mux select line for TIMER6 clock [warm reset insensitive]
0
Select TIMER clock to be TCLKIN
1h
Select TIMER clock to be external 32 KHz clock.(After MUX)
2h
Select TIMER clock to be CLKIN
3h
Reserved
14.7.4.31 CM_SYSCLK23_CLKSEL Register
The CM_SYSCLK23_CLKSEL register selects the divider value for SYSCLK23. It is shown and
described in the figure and table below.
Figure 14-48. CM_SYSCLK23_CLKSEL Register
31
3
2
0
Reserved
CLKSEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-63. CM_SYSCLK23_CLKSEL Register Field Descriptions
Bit
Field
Value
Description
31-3
Reserved
0
Reserved
2-0
CLKSEL
Selects the divider value [warm reset insensitive]
0
Select SYS_CLK divided by 1
1h
Select SYS_CLK divided by 2
2h
Select SYS_CLK divided by 3
3h
Select SYS_CLK divided by 4
4h
Select SYS_CLK divided by 5
5h
Select SYS_CLK divided by 6
6h
Select SYS_CLK divided by 7
7h
Select SYS_CLK divided by 8
1446
Power, Reset, and Clock Management (PRCM) Module
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated
Содержание TMS320C6A816 Series
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