Preliminary
Registers
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14.7.11.23 CM_ALWON_I2C_0_CLKCTRL Register
The CM_ALWON_I2C_0_CLKCTRL register manages the I2C_0 clocks. It is shown and described in
the figure and table below.
Figure 14-103. CM_ALWON_I2C_0_CLKCTRL Register
31
18 17
16 15
2
1
0
Reserved
IDLEST
Reserved
MODULEMODE
R-0
R-3h
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-118. CM_ALWON_I2C_0_CLKCTRL Register Descriptions
Bit
Field
Value
Description
31-18
Reserved
0
Reserved
17-16
IDLEST
Module idle status.
0
Module is fully functional, including OCP
1h
Module is performing transition: wakeup, or sleep, or sleep abortion
2h
Module is in Idle mode (only OCP part). It is functional if using separate
functional clock
3h
Module is disabled and cannot be accessed
15-2
Reserved
0
Reserved
1-0
MODULEMODE
Control the way mandatory clocks are managed.
0
Module is disabled by software. Any OCP access to module results in an
error, except if resulting from a module wakeup (asynchronous wakeup).
1h
Reserved
2h
Module is explicitly enabled. Interface clock (if not used for functions) may
be gated according to the clock domain state. Functional clocks are
guarantied to stay present. As long as in this configuration, power domain
sleep transition cannot happen.
3h
Reserved
1500
Power, Reset, and Clock Management (PRCM) Module
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated
Содержание TMS320C6A816 Series
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