Preliminary
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Registers
20.9.1.24 USBSS IRQ_DMA_ENABLE_0 Register (IRQDMAENABLE0)
The USBSS IRQ_DMA_ENABLE_0 register (IRQDMAENABLE0) contains 32 enables. Sixteen enables
are assigned to the 16 endpoints associated with the tx_pkt_cmp_0 interrupt and 16 enables are
assigned to the 16 endpoints associated with the rx_pkt_cmp_0 interrupt. Endpoint 0 for both the tx and
rx does not exist; but it is included for completeness of this register.
If the enable is set; then that specific endpoint can generate an interrupt if the event pending count has
exceeded the threshold.
If the enable is cleared; then that specific endpoint cannot generate an interrupt regardless if the event
pending count has exceeded the threshold or not. The USBSS IRQ_DMA_ENABLE_0 Register is
shown in
and described in
.
Figure 20-45. USBSS IRQ_DMA_ENABLE_0 Register (IRQDMAENABLE0)
31
18
17
16
dma_en_rx0_15
dma_en_rx0_1
Reserv
ed
R/W-0
R-0
15
3
2
1
0
dma_en_tx0_15
dma_en_tx0_2
dma_en_tx0_1
Reserv
ed
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20-55. USBSS IRQ_DMA_ENABLE_0 Register (IRQDMAENABLE0) Field Descriptions
Bits
Field
Description
31-18
dma_en_rx0_15
DMA threshold enable value for rx_pkt_cmp_0 for USB0 endpoint 15.
17
dma_en_rx0_1
DMA threshold enable value for rx_pkt_cmp_0 for USB0 endpoint 1.
16
Reserved
Always read as 0. Writes have no effect.
15-3
dma_en_tx0_15
DMA threshold enable value for tx_pkt_cmp_0 for USB0 endpoint 15.
2
dma_en_tx0_2
DMA threshold enable value for tx_pkt_cmp_0 for USB0 endpoint 2.
1
dma_en_tx0_1
DMA threshold enable value for tx_pkt_cmp_0 for USB0 endpoint 1.
0
Reserved
Always read as 0. Writes have no effect.
1845
SPRUGX9 – 15 April 2011
Universal Serial Bus (USB)
© 2011, Texas Instruments Incorporated
Содержание TMS320C6A816 Series
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