Preliminary
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Registers
14.7.4.24 CM_AUDIOCLK_MCBSP_CLKSEL Register
The CM_AUDIOCLK_MCBSP_CLKSEL register selects the Mux select line for McBSP audio clock. It is
shown and described in the figure and table below.
Figure 14-41. CM_AUDIOCLK_MCBSP_CLKSEL Register
31
2
1
0
Reserved
CLKSEL
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-56. CM_AUDIOCLK_MCBSP_CLKSEL Register Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1-0
CLKSEL
Selects the Mux select line for McASP0 audio clock [warm reset insensitive]
0
Select McASP2 audio clock to be SYSCLK20
1h
Select McASP2 audio clock to be SYSCLK21
2h
Select McASP2 audio clock to be SYSCLK22
3h
Reserved
14.7.4.25 CM_TIMER1_CLKSEL Register
The CM_TIMER1_CLKSEL register selects the Mux select line for TIMER1 clock. It is shown and
described in the figure and table below
Figure 14-42. CM_TIMER1_CLKSEL Register
31
2
1
0
Reserved
CLKSEL
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-57. CM_TIMER1_CLKSEL Register Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1-0
CLKSEL
Selects the Mux select line for TIMER1 clock [warm reset insensitive]
0
Select TIMER clock to be TCLKIN
1h
Select TIMER clock to be external 32 KHz clock.(After MUX)
2h
Select TIMER clock to be CLKIN
3h
Reserved
1443
SPRUGX9 – 15 April 2011
Power, Reset, and Clock Management (PRCM) Module
© 2011, Texas Instruments Incorporated
Содержание TMS320C6A816 Series
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