Preliminary
Registers
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18.4.16 WDT_WIRQENCLR Register
IRQ enable clear per-event interrupt enable bit vector, line 0. Write 1 to clear (disable interrupt).
Readout equal to corresponding _SET register.
Figure 18-19. WDT_WIRQENCLR Register
31
2
1
0
Reserved
ENABLE_DLY
ENABLE_OVF
R-0
R/W1C-0
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-27. WDT_WIRQENCLR Register Field Descriptions
Bits
Field
Description
31-2
Reserved
Write 0s for future compatibility. Reads return 0.
1
ENABLE_DLY
Enable for delay event
Read 0: Interrupt disabled (masked)
Write 0: No action
Write 1: Disable interrupt.
Read 1: Interrupt enabled
0
ENABLE_OVF
Enable for overflow event
Read 0: Interrupt disabled (masked)
Write 0: No action
Write 1: Disable interrupt.
Read 1: Interrupt enabled
1678
Watchdog Timer
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated
Содержание TMS320C6A816 Series
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