Preliminary
Registers
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6.3.2.74 RGB_2_xvYCC RGB Input Offset Register (RGB_OFFSET_UP)
The RGB_2_xvYCC RGB input offset register is shown in
and described in
.
Figure 6-96. RGB_2_xvYCC RGB Input Offset Register (RGB_OFFSET_UP)
31
8
7
0
Reserved
RGB_OFFS_H
R-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-105. RGB_2_xvYCC RGB Input Offset Register (RGB_OFFSET_UP) Field Descriptions
Bit
Field
Description
31-8
Reserved
Reserved
7-0
RGB_OFFS_H
Input RGB offset value upper byte (override internal CSC value when program reg
RGB_2_XVYCC.XV_CO_OV = 1)
778
High-Definition Multimedia Interface (HDMI)
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated
Содержание TMS320C6A816 Series
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