Preliminary
Registers
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14.7.11.5 CM_MMUCFG_CLKSTCTRL Register
This register enables the domain power state transition. It controls the software supervised clock
domain state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per
clock input of the domain.
Figure 14-85. CM_MMUCFG_CLKSTCTRL Register
31
9
8
7
2
1
0
Reserved
CLKACTIVITY_MMU_CFG_GCLK
Reserved
CLKTRCTRL
R-0
R-0
R-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-100. CM_MMUCFG_CLKSTCTRL Register Field Descriptions
Bit
Field
Value
Description
31-9
Reserved
0
Reserved
8
CLKACTIVITY_MMU_CFG_GCLK
This field indicates the state of the MMU_CFG_GCLK clock
in the domain.
0
Corresponding clock is gated
1
Corresponding clock is active
7-2
Reserved
0
Reserved
1-0
CLKTRCTRL
Controls the clock state transition of the MMU CFG clock
domain.
0
Reserved
1h
SW_SLEEP: Start a software forced sleep transition on the
domain.
2h
SW_WKUP: Start a software forced wake-up transition on
the domain.
3h
Reserved
1482
Power, Reset, and Clock Management (PRCM) Module
SPRUGX9 – 15 April 2011
© 2011, Texas Instruments Incorporated
Содержание TMS320C6A816 Series
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