Texas Instruments TMS320C6A816 Series, Техническое справочное руководство

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Preliminary
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Clock Management
14.4 Clock Management
PRCM provides a centralized control for the generation, distribution and gating of most clocks in the
device. PRCM gathers externally clocks and device internally generated clocks (FAPLL clocks) for
distribution to the other modules in the device. PRCM module manages system clock generation.
14.4.1 Terminology
The PRCM produces two types of clock: interface and functional clocks.
Interface clocks: these clocks primarily provide clocking for the system interconnect modules and the
portions of device's functional modules which interface to the system interconnect modules. In most
cases, the interface clock supplies the functional module's system interconnect interface and registers.
For some modules, interface clock is also used as functional clock. In this specification, interface clocks
are represented by blue lines.
Functional clock: this clock supplies the functional part of a module or a sub-system. In some cases, a
module or a subsystem may require several functional clocks: 1 or several main functional clock(s), 1 or
several optional clock(s). A module needs its main clock(s) to be operational. Optional clocks are used
for specific features and can be shutdown without stopping the module.
14.4.2 External Clock Sources to PRCM
The Device requires the following clocks: The 32 kHz frequency is used for low frequency operation. It
supplies the clock to the RTC. The MAIN PLL CLOCKS are the source clocks for the C674x DSP,
Cortex™-A8, and all the interconnect clocks. The DDR PLL CLOCKS are the source clocks for DDR.
The VIDEO PLL CLOCKS are the source clocks for HD-DSS. The AUDIO PLL CLOCKS are the source
clocks for McASPs, McBSPs. The Device delivers four clock signals to external devices:
Output clock SYSCLK_OUT can deliver clock outputs of each PLL. CM_CLKOUT_CTRL Register
controls the Clock selection and division ratio.
Table 14-17. External Clock Sources to PR
Clock name Source Destination Description
Main_pll_clock1 Main PLL PRCM Clock input from Main PLL (Flying adder Synthesizer 1)
Main_pll_clock2 Main PLL PRCM Clock input from Main PLL (Flying adder Synthesizer 2)
Main_pll_clock3 Main PLL PRCM Clock input from Main PLL (Flying adder Synthesizer 3)
Main_pll_clock4 Main PLL PRCM Clock input from Main PLL (Flying adder Synthesizer 4)
DDR_pll_clock1 DDR PLL PRCM Clock input from DDR PLL (Flying adder Synthesizer 1)
DDR_pll_clock2 DDR PLL PRCM Clock input from DDR PLL (Flying adder Synthesizer 2)
DDR_pll_clock3 DDR PLL PRCM Clock input from DDR PLL (Flying adder Synthesizer 3)
Video_pll_clock1 Video PLL PRCM Clock input from Video PLL (Flying adder Synthesizer 1)
Video_pll_clock2 Video PLL PRCM Clock input from Video PLL (Flying adder Synthesizer 2)
Video_pll_clock3 Video PLL PRCM Clock input from Video PLL (Flying adder Synthesizer 3)
Audio_pll_clock1 Audio PLL PRCM Clock input from Audio PLL (Flying adder Synthesizer 1)
Audio_pll_clock2 Audio PLL PRCM Clock input from Audio PLL (Flying adder Synthesizer 2)
Audio_pll_clock3 Audio PLL PRCM Clock input from Audio PLL (Flying adder Synthesizer 3)
Audio_pll_clock4 Audio PLL PRCM Clock input from Audio PLL (Flying adder Synthesizer 4)
Audio_pll_clock5 Audio PLL PRCM Clock input from Audio PLL (Flying adder Synthesizer 5)
32 KHz External PRCM 32 kHz clock
CLKIN External PRCM 27 MHz clock
TCLKIN External PRCM Timer clock
PCI_CLK External PRCM Clock input from Main PLL (Flying adder Synthesizer 5)
SYSCLK_OUT PRCM External Observation clock
1409 SPRUGX9 – 15 April 2011 Power, Reset, and Clock Management (PRCM) Module
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