Preliminary
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Registers
17.3.7 Timer IRQENABLE Clear Register (IRQENABLE_CLR)
Component interrupt request enable.
Write 1 to clear (disable interrupt).
Readout equal to corresponding _SET register.
Figure 17-13. Timer IRQENABLE Clear Register (IRQENABLE_CLR)
31
16
Reserved
R-0
15
3
2
1
0
Reserved
TCAR_EN_FLAG
OVF_EN_FLAG
MAT_EN_FLAG
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-13. Timer IRQENABLE Clear Register (IRQENABLE_CLR) Field Descriptions
Bit
Field
Value
Description
31-3
Reserved
0
Reserved
2
TCAR_EN_FLAG
IRQ enable for Compare
R0
IRQ event is disabled
W0
No action
R1
IRQ event is enabled
W1
Clear IRQ enable
1
OVF_EN_FLAG
IRQ enable for Overflow
R0
IRQ event is disabled
W0
No action
R1
IRQ event is enabled
W1
Clear IRQ enable
0
MAT_EN_FLAG
IRQ enable for Match
R0
IRQ event is disabled
W0
No action
R1
IRQ event is enabled
W1
Clear IRQ enable
1651
SPRUGX9 – 15 April 2011
Timers
© 2011, Texas Instruments Incorporated
Содержание TMS320C6A816 Series
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