RX610 Group
REVISION HISTORY
R01UH0032EJ0120 Rev.1.20
Page 1002 of 1006
Feb 20, 2013
Rev.
Data
Description
Rev.
Page
1.20
Feb 20, 2013
32
35
43
49 to 53
1. Overview
Table 1.2 List of Products, product lineup added
Figure 1.3 Pin Assignment of the 176-pin LFBGA, changed
Table 1.3 List of Pins and Pin Functions (176-Pin LFBGA), changed
Table 1.5 Pin Functions, description on bus control changed, note added
73
2. CPU
2.5.5 Notes on Arrangement of Instruction Code, description changed
104 to 124
125 to 153
5. I/O register
Table 5.1 List of I/O Registers (Address Order), changed
Table 5.2 List of I/O Registers (Bit Order), changed
164
164
7. Clock Generation Circuit
7.3.1 Connecting a Crystal Resonator, description deleted
Figure 7.3 Equivalent Circuit of Crystal Resonator, description deleted
184
189
8. Low Power Consumption
8.2.7 Deep Standby Interrupt Enable Register (DPSIER), description changed
8.5.1.1 Transition to Sleep Mode, description changed
263 to 264
297
298
11. Buses
11.3.1 CSi Control Register (CSiCNT) (i = 0 to 7), EMODE bit description changed
11.5.5.3 Restrictions in Relation to RMPA and String-Manipulation Instructions, description
changed
11.5.5.5 Restriction on Instruction Code, description changed
359
360
13. Data Transfer Controller (DTC)
Figure 13.11 Example of DTC Operation Timing 2 (Short-Address Mode, Block Transfer
Mode, Block Size = 3), title changed
Figure 13.12 Example of DTC Operation Timing 3 (Short-Address Mode, Chain Transfer)
and Figure 13.13 Example of DTC Operation Timing 4 (Full-Address Mode, Normal
Transfer Mode, Repeat Transfer Mode), changed
447 to 450
14. I/O Ports
14.6 I/O Port Configuration, added
624
637
638
645
646
653
654
20. Serial Communications Interface (SCI)
20.2.7 Serial Status Register (SSR), changed
Table 20.9 BRR Settings for Various Bit Rates (Clock Synchronous Mode), changed
Table 20.11 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S =
372), changed
Figure 20.7 Example of SCI Initialization Flowchart (Asynchronous Mode) , note added
Figure 20.8 Example of Operation for Serial Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit), changed
Figure 20.14 Example of SCI Initialization Flowchart (Clock Synchronous Mode), note
added
Figure 20.15 Example of Operation for Serial Transmission in Clock Synchronous Mode
680
681
21. CRC Calculator (CRC)
21.2.1 CRC Control Register (CRCCR), note deleted
21.2.3 CRC Data Output Register (CRCDOR), changed