RX610 Group
22. I
2
C Bus Interface (RIIC)
R01UH0032EJ0120 Rev.1.20
Page 704 of 1006
Feb 20, 2013
NF[1:0] Bits (Noise Filter Stage Selection)
These bits are used to select the number of stages of the digital noise filter.
Note: Set the noise range to be filtered out by the noise filter within a range less than the SCLn line high-level period or
low-level period. If the noise range is set to a value of (SCL clock width: high-level period or low-level period,
whichever is shorter)
−
[1.5 internal reference clock (IIC
φ
) analog noise filter: 120 ns (reference value)]
or more, the SCL clock is regarded as noise by the noise filter function of the RIIC, which may prevent the RIIC
from operating normally.
ACKBR Bit (Receive Acknowledge)
This bit is used to store the acknowledge bit information received from the receive device in transmit mode.
[Setting condition]
•
When a 1 is received as the acknowledge bit with the TRS bit in ICCR2 set to 1
[Clearing conditions]
•
When a 0 is received as the acknowledge bit with the TRS bit in ICCR2 set to 1
•
When 1 is written to the IICRST bit in ICCR1 while the ICE bit in ICCR1 is 0 (RIIC reset)
ACKBT Bit (Transmit Acknowledge)
This bit is used to set the bit to be sent at the acknowledge timing in receive mode.
[Setting condition]
•
When 1 is written to this bit with the ACKWP bit set to 1
[Clearing conditions]
•
When 0 is written to this bit with the ACKWP bit set to 1
•
When stop condition issuance is detected (when a stop condition is detected with the SP bit in ICCR2 set to 1)
•
When 1 is written to the IICRST bit in ICCR1 while the ICE bit in ICCR1 is 0 (RIIC reset)
Note: The ACKBT bit must be modified while the ACKWP bit is 1. If the ACKBT bit is modified with the ACKWP bit
cleared to 0, writing to the ACKBT bit is disabled.
ACKWP Bit (ACKBT Write Protect)
This bit is used to control the modification of the ACKBT bit.
RDRFS Bit (RDRF Flag Set Timing Selection)
This bit is used to select the RDRF flag set timing in receive mode and also to select whether to hold the SCLn line low
at the falling edge of the eighth SCL clock cycle.
When the RDRFS bit is 0, the SCLn line is not held low at the falling edge of the eighth SCL clock cycle, and the RDRF
flag is set to 1 at the rising edge of the ninth SCL clock cycle.
When the RDRFS bit is 1, the RDRF flag is set to 1 at the rising edge of the eighth SCL clock cycle and the SCLn line is
held low at the falling edge of the eighth SCL clock cycle. The low-hold of the SCLn line is released by writing a value
to the ACKBT bit.
After data is received with this setting, the SCLn line is automatically held low before the acknowledge bit is sent. This
enables processing to send ACK (ACKBT = 0) or NACK (ACKBT = 1) according to receive data.
