RX610 Group
12. DMA Controller (DMAC)
R01UH0032EJ0120 Rev.1.20
Page 306 of 1006
Feb 20, 2013
Bit
Symbol
Bit Name
Description
R/W
b27 to b24
OPSEL[3:0]
Operand Transfer Data Count Select
b27 b26 b25 b24
0
0
0
0: Single data
0
0
0
1: 2 data
0
0
1
0: 4 data
0
0
1
1: 8 data
0
1
0
0: 16 data
0
1
0
1: 32 data
0
1
1
0: 64 data
0
1
1
1: 128 data
Do not write other values.
R/W
b31 to b28
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
DMMOD is used to set the addition direction of transfer source and destination addresses and to set the size of transfer data.
Do not set DMMOD during data transfer, but set it while the DMAC is not active or DMA transfer is disabled.
Access this register with 32 bits.
DMOD[2:0] Bits (Transfer Destination Address Addition Direction Select)
SMOD[2:0] Bits (Transfer Source Address Addition Direction Select)
These bits select the addition direction of transfer source and destination addresses during DMA transfer.
When "rotate" is selected, address is added in the plus direction and is returned to the value specified at the beginning of DMA
transfer when single-operand transfer is completed.
Transfer source and destination addresses increase or decrease according to the addition direction and data size settings as
shown in table 12.3.
Table 12.3 Address Increase/Decrease According to Addition Direction and Data Size
SZSEL[2:0] Bits
SMOD[2:0] Bits/DMOD[2:0] Bits
000b (Fixed)
001b (Plus)
010b (Minus)
011b (Rotate)
000b (8 bits)
±
0
+1
-1
+1
001b (16 bits)
±
0
+2
-2
+2
010b (32 bits)
±
0
+4
-4
+4
SZSEL[2:0] Bits (Transfer Data Size Select)
The SZSEL[2:0] bits select the bit length of transfer data.
OPSEL[3:0] Bits (Operand Transfer Data Count Select)
The OPSEL[3:0] bits select the data count of single-operand transfer.
When the operand transfer system is used, data of the volume specified by the OPSEL[3:0] bits is continuously
transferred as a single operand.
When the nonstop transfer system is used, data of the volume specified by the DMA current transfer byte count register
(DMCBC) of DMACm is continuously transferred independently of the OPSEL[3:0] setting.