RX610 Group
20. Serial Communications Interface (SCI)
R01UH0032EJ0120 Rev.1.20
Page 640 of 1006
Feb 20, 2013
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1 bit = Base clock
×
16
Average transfer rate = 3 MHz/16 = 187.5 kbps
4 MHz
3 MHz
SCK5
internal base clock
= 4 MHz
×
3/4
= 3 MHz (average)
Base clock
TMO0 output
4 MHz
Clock enable
TMO1 output
This figure shows an example when TMR clock is input to SCI5.
When generating 187.5 kbps of TMR average transfer rate for PCLK = 32 MHz:
(1) Generate a frequency of 4 MHz using TMO0 as the base clock.
(2) Set TMO1 in the compare match count of TCNT in TMR0 and generate 3/4 clock enable to set an
average transfer rate of 3 MHz/16 = 187.5 kbps.
Setting examples of TMR and SCI
TMR0.TCR = 08h (TMR0.TCNT is cleared at compare match in TMR0.TCORA, the count is incremented at rising edge of PCLK/2)
TMR0.TCCR = 09h
TMR1.TCR = 08h (TMR1.TCNT is cleared at compare match in TMR1.TCORA, the count is incremented at compare match A in TMR0.TCNT)
TMR1.TCCR = 18h
TMR0.TCSR = 09h (Low is output at compare match in TMR0.TCORA, High is output at compare match in TMR0.TCORB)
TMR1.TCSR = 09h (Low is output at compare match in TMR1.TCORA, High is output at compare match in TMR1.TCORB)
TMR0.TCNT = TMR1.TCNT = 0
TMR0.TCORA = 03h, TMR0.TCORB = 01h
TMR1.TCORA = 03h, TMR1.TCORB = 00h
SCI5.SEMR = 10h
When using SCI6, set TM02 as the base clock and TMO3 as clock enable.
Base clock
Clock enable
TMO0
TMO1
SCI5
SCK5
TMR (unit 0)
Figure 20.3 Example of Average Transfer Rate Setting when TMR Clock is Input
