RX610 Group
12. DMA Controller (DMAC)
R01UH0032EJ0120 Rev.1.20
Page 321 of 1006
Feb 20, 2013
12.2.15
DMA Arbitration Status Register (DMASTS)
Address: 0008 251Bh
b7
b6
b5
b4
b3
b2
b1
b0
Value after reset:
0
0
0
0
0
0
0
0
DASTS0
DASTS1
DASTS2
DASTS3
—
—
—
—
Bit
Symbol
Bit Name
Description
R/W
b3 to b0
Reserved
These bits are always read as 0. Do not write to this bit.
R
b4
DASTS3
Channel 3 Arbitration Status Flag
0: Data transfer is not in progress
1: Data transfer is in progress
(during operand transfer or nonstop transfer)
R
b5
DASTS2
Channel 2 Arbitration Status Flag
R
b6
DASTS1
Channel 1 Arbitration Status Flag
R
b7
DASTS0
Channel 0 Arbitration Status Flag
R
DMASTS indicates data transfer status of each channel.
DASTSm Flag (Channel m Arbitration Status Flag) (m = 0 to 3)
When data transfer (single-operand transfer or nonstop transfer) of channel m is started, the corresponding DASTSm flag
is set to 1 and is cleared to 0 when the data transfer is completed.
[Setting conditions]
•
In the case of operand transfer, the start of transfer for an operand
•
In the case of non-stop transfer, the start of DMA transfer
[Clearing condition]
•
The completion of transfer for a single operand or of DMA transfer