RX610 Group
13. Data Transfer Controller (DTC)
R01UH0032EJ0120 Rev.1.20
Page 355 of 1006
Feb 20, 2013
13.4.4
Repeat Transfer Mode
This mode allows 1-byte, 1-word, or 1-longword data transfer on a single startup source.
Specify either transfer source or transfer destination for the repeat area by the DTS bit in MRB. The transfer count can be
set to 1 to 256. When the specified-count transfer is completed, the initial value of the address register specified in the
transfer counter and the repeat area is restored and transfer is repeated. The other address register is incremented or
decremented continuously or remains unchanged.
When the transfer counter CRAL is decreased to 00h in repeat transfer mode, the CRAL value is updated to the value set
in CRAH. Thus the transfer counter does not become 00h, which inhibits generation of interrupt request to the CPU when
the DISEL bit in MRB is set to 0 (an interrupt request to the CPU is generated when specified data transfer is completed).
Table 13.8 lists the register functions in repeat transfer mode, and figure 13.7 shows the memory map of repeat transfer
mode.
Table 13.8 Register Functions in Repeat Transfer Mode
Register
Description
Value Written Back by Writing Transfer Data
When CRAL is not 1
When CRAL is 1
SAR
Transfer source
address
Increment/decrement/fixed
*
(When the DTS bit in MRB is 0)
Increment/decrement/fixed
*
(When the DTS bit in MRB is 1)
SAR register initial value
DAR
Transfer destination
address
Increment/decrement/fixed
*
(When the DTS bit in MRB is 0)
DAR register initial value
(When the DTS bit in MRB is 1)
Increment/decrement/fixed
*
CRAH
Retains transfer count CRAH
CRAH
CRAL
Transfer count A
CRAL - 1
CRAH
CRB
Transfer count B
Not updated
Not updated
Note:
*
Write-back is skipped in address-fixed mode.