RX610 Group
15. 16-Bit Timer Pulse Unit (TPU)
R01UH0032EJ0120 Rev.1.20
Page 497 of 1006
Feb 20, 2013
(2)
Examples of Cascaded Operation
Figure 15.19 shows the operation when counting upon TPU2.TCNT overflow/underflow has been set for TPU1.TCNT,
TPU1.TGRA and TPU2.TGRA have been set as input capture registers, and the rising edge of the TIOCA1 and TIOCA2
pins has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are
transferred to TPU1.TGRA, and the lower 16 bits to TPU2.TGRA.
TPU2.TCNT clock
TPU2.TCNT
FFFFh
0000h
0001h
TIOCA1, TIOCA2
TPU1.TGRA
03A2h
TPU2.TGRA
0000h
TPU1.TCNT clock
TPU1.TCNT
03A1h
03A2h
Figure 15.19 Example of Cascaded Operation (1)
Figure 15.20 shows the operation when counting upon TPU2.TCNT overflow/underflow has been set for TPU1.TCNT,
and phase counting mode has been specified for TPU2.
TPU1.TCNT is incremented by TPU2.TCNT overflow and decremented by TPU2.TCNT underflow.
TCLKC
TPU2.TCNT
FFFD
TPU1.TCNT
0001
TCLKD
FFFE
FFFF
0000
0001
0002
0001
0000
FFFF
0000
0000
Figure 15.20 Example of Cascaded Operation (2)