Renesas RX600 Series, Руководство пользователя

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RX610 Group 11. Buses
R01UH0032EJ0120 Rev.1.20 Page 280 of 1006
Feb 20, 2013
Data Size
8 bits
16 bits
32 bits
Access Address
Number of
Access
4n One
Two
D0
D7
D15
Data Bus
RD#
WR1#/BC1# WR0#/BC0#
First
First
Second
8 bits
8 bits
8 bits
4n+1 One First 8 bits
4n First 16 bits One
4n+1
4n
4n+2 One First 8 bits
4n+3 One First 8 bits
Two
First
Second
8 bits
8 bits
4n+2 First 16 bits One
4n+3
16 bits
16 bits
16 bits
8 bits
8 bits
First
Second
First
Second
Third
4n+1
Two
Three
4n+2
16 bits
16 bits
16 bits
8 bits
8 bits
First
Second
First
Second
Third
4n+3
Two
Three
4n
4n
4n+2
4n+2
4n
4n
4n+2
4n+2
4n+2
4n+4
4n
4n+2
4n
4n+2
4n+4
4n+2
4n+4
4n+2
4n+4
4n+6
(p)
[Legend]
(p): Page access (only when page access is enabled with the PRENB and PWENB bits in CSiMOD)
16 23 24 31
0 7
8 15
0 7
0 7
0 7
0 7
8
15
0 7
8 15 0 7
8
15
0 7
8
15 0 7
24
31
16 23 8 15
0 7
16
23
24
31
8 15 0 7
24
31
8
15
16
23
0 7
D8
Bus Cycle Unit of Data Address
Figure 11.4 Data Alignment (Big Endian) in 16-Bit Bus Space
11.4.2 8-Bit Bus Space
When an 8-bit bus space is selected by the BSIZE[1:0] bits in CSiCNT, the address bus (A23 to A0) output signals for
access to byte units are enabled.
When byte strobe mode is selected, the WR0# pin is valid, and when single write strobe mode is selected, the WR# pin is
valid. In write access, the low level is always output on the WR0# and WR# pins. The BC0#, WR1#, and BC1# pins are
not used.
Page access can occur in access to data in 16- or 32-bit units. The situations in which page access occurs are indicated by
the letter "(p)" in figures 11.5 and 11.6.
The valid positions of data external to the chip and of the control signals are not affected by the endian.