RX610 Group
11. Buses
R01UH0032EJ0120 Rev.1.20
Page 283 of 1006
Feb 20, 2013
11.5
Operation
11.5.1
Timing of External Bus Access
The various periods in the timing charts are described below.
(1) Tw1 to Twn (clock cycles of waiting for a normal read cycle or normal write cycle)
The period Tw1 to Twn is made up of the number of clock cycles between the start of access via the external bus and the
cycle where waiting is completed (described below). The number of cycles is selectable within the range from zero to 31.
Within this period, the timing of CSi#, RD#, WRi#, and WR# assertion (placing the signals at the low level) is
determined by the respective wait settings. Specifically, the periods of waiting are controlled by the CS assertion wait
(CSON), RD assertion wait (RDON), WR assertion wait (WRON), and write-data output wait (WDON) bits of CSi wait
control register 2 (CSiWCNT2). The number of clock cycles for each of these periods of waiting is selectable as a value
from zero to seven counted from the start of bus access. Selectable numbers of cycles are also within the overall number
of clock cycles of waiting for reading or writing.
(2) Tend (clock cycle where the strobe signal is valid)
Tend is the next clock cycle after completion of the period of waiting for a normal cycle of reading or writing or for a
cycle of page reading or page writing. If the number of clock cycles in the period of waiting for a normal cycle of reading
or writing or for a cycle of page reading or page writing is zero, the clock cycle where bus access starts is the clock cycle
where the strobe signal is valid. The RD#, WRi#, and WR# signals are negated in the next clock cycle after the cycle
where the strobe signal is valid. In the case of read access, the clock cycle where the strobe signal is valid becomes the
clock cycle where the data to be read are sampled.
If an external wait is enabled, the wait signal is sampled at the time of the cycle where the strobe signal is valid. The bus
cycle is extended if the wait signal is at the low level. The bus cycle is completed in the next clock cycle if the wait signal
is at the high level. Tend indicates the cycle where sampling of the wait signal starts.
After the first cycle where the strobe signal is valid during page access, second and subsequent page access operations
(point 6. below) start in the next cycle except in cases of write access where a setting (other than zero) for write-data
output extension clock cycles (point 5. below) has been made. If the setting for the RD or WR assertion wait is a value
other than zero, the RD#, WRi#, and WR# signals are negated in the next clock cycle. If the setting is zero, assertion
continues. Furthermore, the CSi# signal continues to be asserted rather than being negated.
