Intel Embedded Intel486, Справочник по аппаратуре

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
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3.3.2 Cache Updating
When a cache miss occurs on a read, the 16-byte block containing the requested information is
written into the cache. Data in the neighborhood of the required data is also read into the cache,
but the exact position of data within the cache line depends on its location in memory with respect
to addresses divisible by 16.
Any area of memory can be cacheable, but any page of memory can be declared not cacheable
by setting a bit in its page table entry. The I/O region of memory is non-cacheable. When a read
from memory is initiated on the bus, external logic can indicate whether the data may be placed
in cache, as discussed in
Chapter 4, “Bus Operation.” If the read is cacheable, the processor at-
tempts to read an entire 16-byte cache line.
The cache unit follows a write-through cache policy. The unit on the IntelDX4 processor can be
configured to be a write-through or write-back cache. Cache line fills are performed only for read
misses, never for write misses. When the processor is enabled for normal caching and write-
through operation, every internal write to the cache (cache hit) not only updates the cache but is
also passed along to the bus interface unit and propagated through the processor bus to memory.
The only conditions under which data in the cache differs from the corresponding data in memory
occur when a processor write cycle to memory is delayed by buffering in the bus interface unit,
or when an external bus master alters the memory area mapped to the internal cache. When the
IntelDX4 processor is enabled for normal caching and write-back operation, an internal write
only causes the cache to be updated. The modified data is stored for the future update of main
memory and is not immediately written to memory.
3.3.3 Cache Replacement
Replacement in the cache is handled by a pseudo-LRU (least recently used) mechanism. This
mechanism maintains three bits for each set in the valid/LRU block, as shown in
Figure 3-5 . The
LRU bits are updated on each cache hit or cache line fill. Each cache line (four per set) also has
an associated valid bit that indicates whether the line contains valid data. When the cache is
flushed or the processor is reset, all of the valid bits are cleared. When a cache line is to be filled,
a location for the fill is selected by simply finding any cache line that is invalid. If no cache line
is invalid, the LRU bits select the line to be overwritten. Valid bits are not set for lines that are
only partially valid.
Cache lines can be invalidated individually by a cache line invalidation operation on the proces-
sor bus. When such an operation is initiated, the cache unit compares the address to be invalidated
with tags for the lines currently in cache and clears the valid bit if a match is found. A cache flush
operation is also available. This invalidates the entire contents of the internal cache unit.
3.3.4 Cache Configuration
Configuration of the cache unit is controlled by two bits in the processor’s machine status register
(CR0). One of these bits enables caching (cache line fills). The other bit enables memory write-
through.
Table 3-2 shows the four configuration options. Chapter 4, “Bus Operation,” gives de-
tails.