Intel Embedded Intel486, Справочник по аппаратуре

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8-13
SYSTEM BUS DESIGN
Bus clock (BCLK) is an output signal derived from the host CPU clock (HCLKCPU). The
HCLKCPU can be divided by 3, 4, 5, 6 or 8 to give clock frequencies ranging between 8.0 and
8.33 MHz. The high or low time of BCLK can be stretched to synchronize it to four conditions.
16-bit master (MASTER1#16) is an input that indicates that a 16-bit EISA or ISA master has con-
trol of the EISA bus. It is sampled twice, at the beginning and at the end of START#. If negated
at the first sampling time but asserted at the second sampling time, then it indicates to the EBC
that a 32-bit EISA master is translating to 16 bits in order to perform burst operations.
16-bit memory (M16#) is a bidirectional open-collector signal that indicates that the ISA memory
is capable of performing 16-bit transfers. It is an output during ISA master cycles in which a host
slave or EISA memory slave is accessed. It is an input during host bus master cycles in which the
EISA/ISA bus is accessed. It is an input during EISA master cycles.
Standard memory read control strobe (SMRDC#) is an output signal that commands the ISA
memory to place data on the data bus. It is asserted during CPU, DMA or EISA/ISA master read
cycles to 16-bit or 8-bit ISA memory slaves when the address range is less than one megabyte. It
behaves like the MRDC# signal.
Standard memory write control strobe (SMWTC#) is an output signal that commands the ISA
memory slave to accept data from the data bus. It is asserted during CPU, DMA or EISA/ISA
master write cycles to 16-bit or 8-bit ISA memory slaves when the address range is less than one
megabyte.
Channel ready (CHRDY) is a bidirectional, open-collector signal which is used by the ISA slaves
to insert wait states. It is an output during ISA master cycles and accesses host bus slaves or EISA
slaves.
No wait states (NOWS#) is an input asserted by ISA slaves to request compressed standard wait
states, and by EISA bus slaves to request compressed or 1.5 BCLK cycles.
System address bits 1 and 0 (SA1, SA0) are the least significant bits of the latched EISA address
bus. They are inputs during ISA bus master cycles and generate appropriate EISA bus or host bus
controls. They are outputs during host bus master cycles and access EISA/ISA slaves. Further,
they are outputs during EISA master cycles to ISA slaves and during DMA accesses to ISA mem-
ory.
System byte high enable (SBHE#) is a bidirectional signal that indicates the validity of the high
byte on the EISA bus. It is an input during ISA bus master cycles and an output during host ac-
cesses to EISA/ISA slave. Further, it is an output during EISA master cycles to ISA slaves and
during DMA accesses to ISA memory.
Refresh (REFRESH#) is an input which indicates that the ISP is performing a refresh cycle. Dur-
ing refresh cycles the EBC generates the MRDC#, CMD# and other host bus signals to refresh
the entire system’s DRAM memory.
8.3.5 EBC and ISP Interface
The EBC and ISP have a tightly coupled interface, and they interact with the host bus requests,
DMA status, EISA bus master size, and other control and status signals described below: