Intel Embedded Intel486, Справочник по аппаратуре

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4-19
BUS OPERATION
4.3.2.2 Terminating Multiple and Burst Cycle Transfers
The Intel486 processor deasserts BLAST# for all but the last cycle in a multiple cycle transfer.
BLAST# is deasserted in the first cycle to inform the external system that the transfer could take
additional cycles. BLAST# is asserted in the last cycle of the transfer to indicate that the next time
BRDY# or RDY# is asserted the transfer is complete.
BLAST# is not valid in the first clock of a bus cycle. It should be sampled only in the second and
subsequent clocks when RDY# or BRDY# is asserted.
The number of cycles in a transfer is a function of several factors including the number of bytes
the Intel486 processor needs to complete an internal request (1, 2, 4, 8, or 16), the state of the bus
size inputs (BS8# and BS16#), the state of the cache enable input (KEN#) and the alignment of
the data to be transferred.
When the Intel486 processor initiates a request, it knows how many bytes are transferred and if
the data is aligned. The external system must indicate whether the data is cacheable (if the transfer
is a read) and the width of the bus by returning the state of the KEN#, BS8# and BS16# inputs
one clock before RDY# or BRDY# is asserted. The Intel486 processor determines how many cy-
cles a transfer will take based on its internal information and inputs from the external system.
BLAST# is not valid in the first clock of a bus cycle because the Intel486 processor cannot de-
termine the number of cycles a transfer will take until the external system asserts KEN#, BS8#
and BS16#. BLAST# should only be sampled in the second T2 state and subsequent T2 states of
a cycle when the external system asserts RDY# or BRDY#.
The system may terminate a burst cycle by asserting RDY# instead of BRDY#. BLAST# remains
deasserted until the last transfer. However, any transfers required to complete a cache line fill fol-
low the burst order; for example, if burst order was 4, 0, C, 8 and RDY# was asserted after 0, the
next transfers are from C and 8.
4.3.2.3 Non-Cacheable, Non-Burst, Multiple Cycle Transfers
Figure 4-12 illustrates a two-cycle, non-burst, non-cacheable read. This transfer is simply a se-
quence of two single cycle transfers. The Intel486 processor indicates to the external system that
this is a multiple cycle transfer by deasserting BLAST# during the second clock of the first cycle.
The external system asserts RDY# to indicate that it will not burst the data. The external system
also indicates that the data is not cacheable by deasserting KEN# one clock before it asserts
RDY#. When the Intel486 processor samples RDY# asserted, it ignores BRDY#.