Intel Embedded Intel486, Справочник по аппаратуре

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
10-20
When the resistor matches the line impedance, the reflection coefficient at the load approaches
zero, and no reflection occurs. One useful approach is to place the termination as close to the
loading device as possible.
Parallel terminated lines are used to achieve optimum circuit performance and to drive distributed
loads, which is an important benefit of using parallel terminations.
There are two significant advantages of using the parallel termination. First, it provides an undis-
tributed waveform along the entire line. Second, when a long line is loaded in parallel termina-
tion, it does not affect the rise and fall time or the propagation delay of the driving device. Note
that parallel termination can also be used with wire wrap and backplane wiring where the char-
acteristic impedance is not exactly defined. If the designer approximates the characteristic imped-
ance, the reflection coefficient is very small. This results in minimum overshoot and ringing.
Parallel termination is not recommended for characteristic impedances of less than 100 ohms be-
cause of large DC current requirements.
Thevenin’s Equivalent Termination
This technique is an extension of parallel termination technique. It consists of connecting one re-
sistor from the line to the ground and another from the line to the V
CC
. Each resistor has a value
of twice the characteristic impedance of the line, so the equivalent resistance matches the line im-
pedance. This scheme is shown in
Figure 10-15 .
Figure 10-15. Thevenin’s Equivalent Circuit
If there were no logic devices present, the line would be placed halfway between the V
CC
and the
V
SS
. When the logic device is driving the line, a portion of the required current is provided by the
V
CC
Receiver
Driver