Intel Embedded Intel486, Справочник по аппаратуре

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PERIPHERAL SUBSYSTEM
Bus control logic should implement recovery to eliminate bus contention. The logic generates a
RECOV signal until the data from the previous read floats. It may or may not be possible to en-
force this recovery with the hardware counter. The hardware counter method may not be feasible
when recovery times are too fast for the hardware counter (i.e., when recovery time is in nano-
seconds). In this case, recovery time can be enforced in software using NOPs and delay loops or
using a programmable timer.
The advantages of using hardware-enforced recovery are transparency and reliability. When
moving to higher processor clock speeds, no change is needed in the I/O device drivers. For these
reasons, hardware enforced I/O recovery time is recommended.
7.2.7 Write Buffers and I/O Cycles
The Intel486 processor contains four write buffers to enhance the performance of consecutive
writes to memory. Writes are driven onto the external bus in the same order in which they are
received by the write buffers. Under certain conditions, a memory read is reordered in front of
the writes pending in the write buffer even though the writes occurred earlier in program execu-
tion (see
Chapter 4, “Bus Operation” for details).
However, I/O cycles must be handled in a different manner by the write buffers. I/O reads are
never reordered in front of buffered memory writes. This ensures that the Intel486 processor up-
dates all memory locations before reading status from an I/O device.
The Intel486 processor never buffers single I/O writes. When processing an I/O write instruction
(OUT, OUTS), internal execution stops until the I/O write actually completes on the external bus.
This allows time for the external system to drive an invalidate into the Intel486 processor or to
mask interrupts before the processor continues to the instruction following the write instruction.
Repeated OUTS (REP OUTS) instructions are buffered and the next instruction is not executed
until the REP OUTS finishes executing.
7.2.7.1 Write Buffers and Recovery Time
The write buffers, in association with the cache, have certain implications for I/O device recovery
times. Back-to-back write recovery times must be guaranteed by explicitly generating a read cy-
cle to a non-cacheable area in between the writes. Since the Intel486 processor does not buffer
I/O writes, the inserted read does not proceed to the bus until the first write is completed. Then,
the read cycle executes on the external bus. During this time, the I/O device recovers and allows
the next write.
7.2.8 Non-Cacheability of Memory-Mapped I/O Devices
To avoid problems caused by I/O “read arounds,” memory-mapped I/O should not be cached. A
read around occurs when a read cycle is reordered in front of a write cycle. If the memory-mapped
I/O device is cached, it is possible to read the status of the I/O device before all previous writes
to that device are completed. This causes a problem when the read initiates an action requiring
memory to be up-to-date.