Intel Embedded Intel486, Справочник по аппаратуре

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
6-2
occurred, implying that the requested word is present in the cache. If the tags do not match, the
data word is not present in the cache. This is called a cache miss. On a cache hit, the cache data
memory allows a read operation to be completed more quickly from its faster memory than from
a slower main memory access. The hit rate is the percentage of the accesses that are hits, and is
affected by the size and organization of the cache, the cache algorithm used, and the program run-
ning. An effective cache system maintains data in a way that increases the hit rate. Different cache
organizations are discussed later in this chapter. The main advantage of cache is that a larger main
memory appears to have the high speed of a cache. For example, a zero-wait state cache that has
a hit rate of 90 percent makes main memory appear to be zero-wait state memory for 9 out of 10
accesses.
Programs usually address memory in the neighborhood of recently accessed locations. This is
called program locality or locality of reference and it is locality that makes cache systems possi-
ble. Code, data character strings, and vectors tend to be sequentially scanned items or items ac-
cessed repeatedly, and cache helps the performance in these cases. In some cases the program
locality principle does not apply. Jumps in code sequences and context switching are some ex-
amples.
6.2.2 Why Add an External Cache?
System designers must take into account several factors when deciding whether to incorporate a
Level II cache subsystem in an embedded Intel486 processor design. These considerations in-
clude the performance expectations, operating system used, DRAM cycle speed, possible future
upgrades to the initial application, and system costs. Although the Intel486 processor-based per-
sonal computer often required a 256-K to 512-K L2 cache for optimal performance, embedded
applications have a wide variety of performance and cost requirements and their L2 cache needs
vary accordingly. In many applications, an inexpensive 32-K or 64-K cache provides good per-
formance, whereas the additional performance provided by a 512-K cache would be too costly to
justify. When possible, system designers should run the application code on a standard Intel486
processor-based personal computer (assuming the operating system is compatible) and take per-
formance measurements with the L2 cache first enabled, then disabled in the BIOS. Although this
technique for performance evaluation is not perfect, it gives the applications team a good basis
upon which to make design decisions.
6.3 CACHE TRADE-OFFS
Cache efficiency is the cache’s ability to keep the code and data most frequently used by the mi-
croprocessor. Cache efficiency is measured in terms of the hit rate. Another indication of cache
efficiency is system performance; this is the time in which the microprocessor can perform a cer-
tain task and is measured in effective bus cycles. An efficient cache reduces external bus cycles
and enhances overall system performance. Hit rates are discussed in the next section.
Factors that can affect a cache’s performance are:
•
Size: Increasing the cache size allows more items to be contained in the cache. Cost is
increased, however, and a larger cache cannot operate as quickly as a smaller one.