Intel Embedded Intel486, Справочник по аппаратуре

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
10-30
10.4 LATCH-UP
“Latch-up” is triggered when the voltage limits on the I/O pins are exceeded, causing the internal
PN junction to become forward-biased. The following steps ensure the prevention of latch-up.
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Observe the maximum input voltage rating of I/O pins.
•
Never apply power to an Intel486 processor pin or to any device connected to it before
applying power to the Intel486 processor.
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Use good termination techniques to prevent overshoot and undershoot.
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Ensure proper layout to minimize reflections and to reduce noise on the signals.
10.5 CLOCK CONSIDERATIONS
For best performance, the clock signal (CLK) for the Intel486 CPU must be free of noise and
within the specifications listed in the individual Intel486 datasheets. The transmission line effects
must also be considered for the clock paths. These paths should be suitably terminated to mini-
mize signal reflections and prevent overshoot and undershoot.
Skew is an effect of unequal transmission line length and matching. This is very important in a
synchronous system. Long traces add propagation delay. A longer trace or a load placed further
down a trace experiences more delay than a short trace or loads very close to the source. This must
be taken into account when doing the worst case timing analysis. In a system where events must
occur synchronous to a clock signal, it is important to make sure the signal is available to all in-
puts a sufficient amount of time prior to the corresponding clock edge. When performing the
component placement this is one of the considerations that must be accounted for.
To maintain proper logic levels, all digital signal outputs have a maximum load, they are capable
of driving. DC loading is the constant current required by an input in either the high or the low
state. It limits the ability of a device driving the bus to maintain proper logic levels. For an
Intel486 processor-based system, a careful analysis must be performed to ensure that in a worst
case situation no loading limits are exceeded. Even if a bus is loaded slightly beyond its worst
case limit, problems may result if a batch of parts whose input loading is close to maximum is
encountered. The proper logic level may not be maintained and unreliable operation may result.
Marginal loading problems are particularly troublesome, since the effect is often erratic operation
and non-repetitive errors that are difficult to track down. For both the high and low logic levels,
the sum of the currents required by all the inputs and the leakage currents of all outputs (drivers)
on the bus must be added together. This sum must be less than the output capability of the weakest
driver. Since the Intel486 processor is a CHMOS device having negligible DC loading, the main
contributors to D.C. loading are the TTL devices.
The AC or capacitive loading is caused by the input capacitance of each device and limits the
speed at which a device driving a bus signal can change the state from high to low or low to high.
For high-frequency designs, the component and system margins are no longer available to the de-
signer. With less than 1 ns of timing margin, even the small amount of trace capacitance can make
a circuit path critical.
A more accurate calculation of capacitive loading can be derived by modeling the device loads
and system traces as a series of Transmission Lines Theory. Transmission Line Theory provides