Intel Embedded Intel486, Справочник по аппаратуре

Страница: 201 / 334

7-29
PERIPHERAL SUBSYSTEM
7.3 I/O CYCLES
The I/O read and write cycles used in a system are a factor of the I/O control logic implementa-
tion.
Figures 7-13 through 7-16 illustrate an I/O read and write cycle for a typical implementation.
7.3.1 Read Cycle Timing
A new processor read cycle is initiated when ADS# is asserted in T1. The address and status sig-
nals (M/IO# = low, W/R# = low, D/C# = high) are asserted. The IOCYC signal is generated by
the control logic by decoding ADS#, M/IO#, W/R# and D/C#. IOCYC indicates to an external
device that an I/O cycle is pending. The IOR# signal is asserted in the T2 state when IOCYC is
valid and RECOV is inactive. The RECOV signal indicates that the new cycle must be delayed
to meet the I/O device recovery time or to prevent data bus contention. The I/O read signal (IOR#)
signal is not asserted until RECOV is deasserted. Data becomes valid after IOR# is asserted, with
the timing dependent on the number of wait states implemented.
In the example, two wait states are required for the slowest I/O device to do a read, and the bus
control logic keeps IOR# active to meet the minimum active time requirement. The worst case
timing values are calculated by assuming maximum delay in the decode logic and through data
transceivers. The following equations show the fastest possible cycle implementation. Wait
States should be added to meet the access times of the I/O devices used.
Figure 7-13 and 7-14
show the I/O read cycle timing and the critical analysis.
Figure 7-13. I/O Read Timing Analysis
TR
VD
Read Signal Valid Delay
TR
VD
= T
PLDpd
= 10 ns
TD
SU
Read Data Setup Time
TD
SU
= T
BUFpd
+ T
su
†
= 9 + 5 = 14 ns
TD
HD
Read Data Hold Time
TD
HD
= T
HD
†
– T
BUFpd
= 3 – 9 = –6 ns
†
T
SU
= T
22
= Intel486™ processor time (33 MHz)
T
HD
= Intel486 processor read hold time (33 MHz)