EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
7-24
Address select signals are asserted within the range of addresses which is determined by the de-
coded address lines. The relationship between memory and I/O mapping and address decoding is
given by the following equation:
Given thatn = bits to decoder
m = bits to I/O or memory
then
# of chip selects = 2
n
address range = 2
m
= # of least significant address lines
For example, when the address decoder decodes A13 through the most significant address bits,
the least significant 13 address bits A2 to A12 are ignored. Hence the address select can be as-
serted for a 2-Kbyte address range.
For I/O-mapped devices, the maximum I/O space is 64 Kbytes. When using I/O instructions the
block size (range of addresses) for each address select signal is much smaller than the address
space of the memory-mapped devices. The minimum block size is determined according to the
number of addresses being used by the peripheral device.
A typical address decoding circuit for a basic I/O interface implementation is shown in
Figure
7-11
. It uses 74S138. Only one output is asserted at a time. The signal corresponding to the binary
number present at the A, B and C inputs and value of the gate enable signals.
Figure 7-12
shows the internal logic and truth table of the 74S138. It has three enable inputs; two
are active low, and one is active high. All three inputs must be asserted; otherwise the outputs are
deasserted. Since all of the outputs are active low, the selected output is low and the others are
high.
Figure 7-11. I/O Address Example
RDY#
RESET
TIMEOUT
S
D
Q#
Q
ADS#
CPU CLK
A5
A6
A7
A2
A3
A4
M/IO#
D/C#
IO CS (XXE0)
E4
E8
FC
F8
E1
E2
E3
A
B
C
74S138
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