Intel Embedded Intel486, Справочник по аппаратуре

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
10-2
The worst-case power dissipation of any VLSI device is estimated in the following manner:
•
Estimate typical power dissipation for each circuit element:
P
G
: Typical power dissipation for internal logic gates (mW)
P
IO
: Typical power dissipation for I/O buffers (mW)
P
CRAM
: Typical power dissipation for instruction/data cache RAMs (mW)
•
To estimate total typical power dissipation for the device:
(1) P
T
= P
G
+ P
IO
+ P
CRAM
(mW),
where P
T
is the total typical power dissipation (mW)
•
To estimate the worst case power dissipation:
(2) P
d
= P
T
x C
V
(mW),
where P
d
is the worst case power dissipation (mW) and C
V
is a multiplier that is
dependent upon power supply voltage.
Internal logic power dissipation varies with operating frequency and to some extent with wait
states and software. It is directly proportional to supply voltage. Process variations in manufac-
turing also affect the internal logic power dissipation, although to a lesser extent than with the
NMOS processes.
The I/O buffer power dissipation, which accounts for roughly 10 to 25 percent of the overall pow-
er dissipation, varies with the frequency and the supply voltage. It is also affected by the capaci-
tive bus loading. The capacitive bus loading for all output pins is specified in the Intel486
processor family datasheets. The Intel486 processor’s output valid delays increase if these load-
ings are exceeded. The addressing pattern of the software can affect I/O buffer power dissipation
by changing the effective frequency at the address pins. The frequency variations at the data pins
tend to be smaller; a varying data pattern should not cause a significant change in the total power
dissipation.
To calculate the total power dissipated by a system board, the following formulas can be used to
calculate the maximum statistical power:
P
T1
+ P
T
2
+ ... + (P
max1
– P
typical1
)
2
+ (P
max2
– P
typical2
)
2
....
where P
T1
and P
max1
are the typical and maximum power dissipation of each of the integrated
circuits on the board.
10.2.1 Power and Ground Planes
Today’s high-speed CMOS logic devices are susceptible to ground noise and the problems this
noise creates in digital system design. This noise is a direct result of the fast switching speed and
high drive capability of these devices, which are requisites in high-performance systems. Logic
designers can use techniques designed to minimize this problem. One technique is to reduce ca-
pacitance loading on signal lines and provide optimum power and ground planes.
Power and ground lines have inherent inductance and capacitance, which affect the total imped-
ance of the system. Higher impedances reduce current and therefore offer reduced power con-
sumption, while low impedance (ground plane) minimizes problems such as noise and