Intel Embedded Intel486, Справочник по аппаратуре

Страница: 52 / 334

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
3-8
The bus interface unit contains the following architectural features:
•
Address Transceivers and Drivers — The A31–A2 address signals are driven on the
processor bus, together with their corresponding byte-enable signals, BE3#–BE0#. The
high-order 28 address signals are bidirectional, allowing external logic to drive cache
invalidation addresses into the processor.
•
Data Bus Transceivers — The D31–D0 data signals are driven onto and received from the
processor bus (for the Ultra-Low Power Intel486 GX processor, signals D15–D0 comprise
the data bus transceivers).
•
Bus Size Control — Three sizes of external data bus can be used: 32, 16, and 8 bits wide.
Two inputs from external logic specify the width to be used. Bus size can be changed on a
cycle-by-cycle basis. The Ultra-Low Power Intel486 GX does not support dynamic bus
sizing; its external data bus is 16 bits wide.
•
Write Buffering — Up to four write requests can be buffered, allowing many internal
operations to continue without waiting for write cycles to be completed on the processor
bus.
•
Bus Cycles and Bus Control — A large selection of bus cycles and control functions are
supported, including burst transfers, non-burst transfers (single- and multiple-cycle), bus
arbitration (bus request, bus hold, bus hold acknowledge, bus locking, bus pseudo-locking,
and bus backoff), floating-point error signalling, interrupts, and reset. Two software-
controlled outputs enable page caching on a cycle-by-cycle basis. One input and one output
are provided for controlling burst read transfers.
•
Parity Generation and Control — Even parity is generated on writes to the processor and
checked on reads. An error signal indicates a read parity error.
•
Cache Control — Cache control and consistency operations are supported. Three inputs
allow the external system to control the consistency of data stored in the internal cache unit.
Two special bus cycles allow the processor to control the consistency of external cache.
3.2.1 Data Transfers
To support the cache, the bus interface unit reads 16-byte cacheable transfers of operands, in-
structions, and other data on the processor bus and passes them to the cache unit. When cache
contents are updated from an internal source, such as a register, the bus interface unit writes the
updated cache information to the external system. Non-cacheable read transfers are passed
through the cache to the integer or floating-point units.
During instruction prefetch, the bus interface unit reads instructions on the processor bus and
passes them to both the instruction prefetch unit and the cache. The instruction prefetch unit may
then obtain its inputs directly from the cache.
3.2.2 Write Buffers
The bus interface unit has temporary storage for buffering up to four 32-bit write transfers to
memory. Addresses, data, or control information can be buffered. Single I/O-mapped writes are
not buffered, although multiple I/O writes may be buffered. The buffers can accept memory