Intel Embedded Intel486, Справочник по аппаратуре

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
4-28
progressing to the next 32-bit word. For example, a BS16# burst to address 4 has the following
order: 4-6-0-2-C-E-8-A.
4.3.4.3 Interrupted Burst Cycles
Some memory systems may not be able to respond with burst cycles in the order defined in Table
4-8 . To support these systems, the Intel486 processor allows a burst cycle to be interrupted at any
time. The Intel486 processor automatically generates another normal bus cycle after being inter-
rupted to complete the data transfer. This is called an interrupted burst cycle. The external system
can respond to an interrupted burst cycle with another burst cycle.
The external system can interrupt a burst cycle by asserting RDY# instead of BRDY#. RDY# can
be asserted after any number of data cycles terminated with BRDY#.
An example of an interrupted burst cycle is shown in Figure 4-19 . The Intel486 processor imme-
diately asserts ADS# to initiate a new bus cycle after RDY# is asserted. BLAST# is deasserted
one clock after ADS# begins the second bus cycle, indicating that the transfer is not complete.
Figure 4-19. Interrupted Burst Cycle
KEN# need not be asserted in the first data cycle of the second part of the transfer shown in
Figure 4-20 . The cycle had been converted to a cache fill in the first part of the transfer and the
Intel486 processor expects the cache fill to be completed. Note that the first half and second half
of the transfer in
Figure 4-19 are both two-cycle burst transfers.
242202-067
CLK
ADS#
A31–A2
BRDY#
BLAST#
DATA
Ti T1 T2 Ti
To Processor
T2 T1 T2 T2
KEN#
RDY#
104 100 10C 108
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