Intel Embedded Intel486, Справочник по аппаратуре

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10-29
PHYSICAL DESIGN AND SYSTEM DEBUGGING
Electrostatic interference (ESI) is caused by this type of coupling. The charge built on one plate
of the capacitor induces opposite charge on the other. To minimize the ESI, the following steps
should be taken.
•
Separate the signal lines so that the effect of capacitive coupling is negated.
•
Run a ground line between the two lines to cancel the electrostatic fields.
For high-frequency designs, a rule of thumb is to include ground planes under each signal layer.
Ground planes limit the EMI caused by a capacitive coupling between small sections of adjacent
layers that are at equipotentials. Additionally, when the width and the thickness of signal lines
and their distance from the ground is constant, the effect of capacitive coupling upon impedance
remains uniform within approximately ±5 percent across the board. Using fixed impedance does
not reduce capacitive coupling, but it does simplify the modeling of propagation delays and cou-
pling effects. In addition, capacitive coupling can cause interference between layers, so the wires
should be routed orthogonally on neighboring board layers.
10.3.4 Propagation Delay
The propagation delay of a circuit is a function of the loads on the line, the impedance, and the
line segments. The term propagation delay means the signal rise time delay in the entire circuit,
including the delay in the transmission line (which is a function of the dielectric constant).
Also, the printed circuit interconnection adds to the propagation delay of every signal on the wire.
These interconnections not only decrease the operating speed of the circuits, but also cause re-
flection, which produces undershoot and overshoot.
When the propagation delays in the circuit are significant, the design must compensate for the
signal skew. Signal skew occurs when the wire lengths (and thus the propagation delays) between
each source and each corresponding load are unequal.
Another negative aspect of propagation delay is that it causes a generation of race condition. This
condition occurs when two signals must reach the same destination within one clock pulse of one
another. To avoid race conditions, it is necessary to have the signals travel through the same
length traces. But if one route is shorter, the signals arrive at different timings, causing race con-
ditions.
One way to minimize this is by decreasing the length of the interconnections. Overall route
lengths are shorter in multi-layer printed circuit boards than in double-layer boards because
ground and power traces are not present. In addition to adding ground planes, a routing program
can help to shorten the routing paths.
The guidelines discussed thus far are prominent at the higher operating frequencies. Debugging
an Intel486 processor-based system at higher frequencies requires careful layout of the physical
design. This section also covers latch-up and thermal characteristics which are system design
considerations that stem from the device itself.