Intel Embedded Intel486, Справочник по аппаратуре

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EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
8-10
EBC that is asserted high when the ISP is performing DMA or refresh cycles. It is also used to
decode shutdown and interrupt acknowledge cycles.
Host bus ready input (HRDYI#) is an input signal that indicates the termination of a cycle on the
host bus.
Host bus ready output (HRDYO#) is an output signal indicating that the EBC has completed a
cycle. It is asserted when the host is addressing an EISA/ISA slave and the cycle has completed
by appropriate inputs from EXRDY, CHRDY, NOWS#, and DRDY.
Host bus early ready output (HERDYO#) is an early version of the ready output from the EBC
for situations in which HRDYO# does not provide enough setup time.
8.3.3.2 Host Local Memory and I/O Interface
Host bus local memory (HLOCMEM#) is an input signal which indicates that a host bus memory
slave has decoded the current address as its own without preconditioning the HMI/O# signal. If
this signal is asserted on host bus master memory cycles, it prevents an EISA bus cycle from ini-
tiating. This signal is used to determine if the memory is being accessed on the host bus during
EISA/ISA master memory cycles or during DMA cycles.
Host bus local I/O (HLOCIO#) is an input signal which indicates that a host bus I/O slave has
decoded the current address as its own without preconditioning the HMI/O# signal. If this signal
is asserted on host bus master I/O cycles, it prevents EISA bus cycle from initiating. This signal
is used to determine if the I/O device is being accessed on the host bus during EISA/ISA master
I/O cycles.
Host bus stretch (HSTRETCH#) is an input used by host bus slaves during EISA/ISA master cy-
cles to run zero (EISA) wait state cycles. This input can be used during DMA cycles and
EISA/ISA bus master cycles to stretch the low period of the BCLK during the CMD# portion of
the cycle. BCLK remains low until HSTRETCH# is sampled high. This produces a “stalling” ef-
fect of the EISA/ISA master without adding BCLK wait states. If the host memory subsystem is
capable of performing EISA cycles without wait states, then the HSTRETCH# can be pulled high
and no CPU clock-based logic is required for bus master or DMA cycles.
8.3.3.3 Host Bus Acquisition and Release
Host bus hold request (HHOLD) is an output signal which is asserted by the EBC to indicate a
hold request to the host. This occurs when the ISP asserts DHOLD to indicate that an EISA/ISA
bus master wants control or that a DMA device requires service.
Host hold acknowledge (HHLDA) is an input signal to the EBC from the bus master to indicate
that it has relinquished control.
8.3.3.4 Lock, Snoop, and Address Greater than 16 Mbytes
Host bus lock (HLOCK#) is an input signal which is asserted by the host master when a locked
bus cycle is in progress. If the addressed device is on the EISA bus, the signal is propagated to
the LOCK# signal on the EISA bus.