Infineon XC886CLM, Руководство пользователя

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XC886/888CLM
Power Supply, Reset and Clock Management
User’s Manual 7-15 V1.3, 2010-02
Power, Reset and Clock, V 1.0
For different source oscillator, the selection of output frequency f
sys
= 96 MHz is shown
in Table 7-5 .
For the XC886/888, the value of P is fixed to 1. In order to obtain the required f
sys
, the
value of N and K can be selected by bits NDIV and KDIV respectively for different
oscillator inputs. The output frequency must always be configured for 96 MHz.
Table 7-6 shows the VCO ranges in the XC886/888.
The VCO range can be selected by bit VCOSEL. For
f
sys
= 96 MHz and K = 2,
f
vco
=
f
sys
*2 = 192 MHz, VCOSEL must be selected to be 0.
7.3.3 Clock Management
The Clock Management sub-module generates all clock signals required within the
microcontroller from the basic clock. It consists of:
• Basic clock slow down circuitry
• Centralized enable/disable circuit for clock control
Figure 7-7 shows the clock generation from the system frequency f
sys
. In normal running
mode, the typical frequencies of different modules are as follows:
• CPU clock: CCLK, SCLK = 24 MHz
• Fast clock: FCLK = 24 or 48 MHz
• Peripheral clock: PCLK = 24 MHz
• Flash Interface clock: CCLK2 = 48 MHz and CCLK = 24 MHz
For the XC886/888, FCLK is used to clock the MultiCAN at 24 MHz or 48 MHz clock. The
selection of the clock frequency is done via bit CMCON.FCCFG.
Table 7-5 System frequency (
f
sys
= 96 MHz)
Oscillator fosc N P K fsys
On-chip 9.6 MHz 20 1 2 96 MHz
External 8 MHz 24 1 2 96 MHz
6 MHz 32 1 2 96 MHz
4 MHz 48 1 2 96 MHz
Table 7-6 VCO Ranges
VCOSEL f
VCOmin
f
VCOmax
f
VCOFREEmin
f
VCOFREEmax
Unit
0 150 200 20 80 MHz
1 100 150 10 80 MHz
*